Patents by Inventor William E. Ballachino

William E. Ballachino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • M-bit race delay adder and method of operation
    Patent number: 8473541
    Abstract: There is disclosed an M-bit adder capable of receiving a first M-bit argument, a second M-bit argument, and a carry-in (CI) bit. The M-bit adder comprises M adder cells arranged in R rows, wherein a least significant adder cell in a first one of the rows of adder cells receives a first data bit, AX, from the first M-bit argument and a first data bit, BX, from the second M-bit argument, and generates a first conditional carry-out bit, CX(1), and a second conditional carry-out bit, CX(0), wherein the CX(1) bit is calculated assuming a row carry-out bit from a second row of adder cells preceding the first row is a 1 and the CX(0) bit is calculated assuming the row carry-out bit from the second row is a 0.
    Type: Grant
    Filed: August 3, 2009
    Date of Patent: June 25, 2013
    Assignee: STMicroelectronics, Inc.
    Inventor: William E. Ballachino
  • M-BIT RACE DELAY ADDER AND METHOD OF OPERATION
    Publication number: 20100036902
    Abstract: There is disclosed an M-bit adder capable of receiving a first M-bit argument, a second M-bit argument, and a carry-in (CI) bit. The M-bit adder comprises M adder cells arranged in R rows, wherein a least significant adder cell in a first one of the rows of adder cells receives a first data bit, Ax, from the first M-bit argument and a first data bit, Bx, from the second M-bit argument, and generates a first conditional carry-out bit, Cx(1), and a second conditional carry-out bit, Cx(0), wherein the Cx(1) bit is calculated assuming a row carry-out bit from a second row of adder cells preceding the first row is a 1 and the Cx(0) bit is calculated assuming the row carry-out bit from the second row is a 0.
    Type: Application
    Filed: August 3, 2009
    Publication date: February 11, 2010
    Inventor: William E. Ballachino
  • M-bit race delay adder and method of operation
    Patent number: 7571204
    Abstract: There is disclosed an M-bit adder capable of receiving a first M-bit argument, a second M-bit argument, and a carry-in (CI) bit. The M-bit adder comprises M adder cells arranged in R rows, wherein a least significant adder cell in a first one of the rows of adder cells receives a first data bit, AX, from the first M-bit argument and a first data bit, BX, from the second M-bit argument, and generates a first conditional carry-out bit, CX(1), and a second conditional carry-out bit, CX(0), wherein the CX(1) bit is calculated assuming a row carry-out bit from a second row of adder cells preceding the first row is a 1 and the CX(0) bit is calculated assuming the row carry-out bit from the second row is a 0.
    Type: Grant
    Filed: September 21, 2000
    Date of Patent: August 4, 2009
    Assignee: STMicroelectronics, Inc.
    Inventor: William E. Ballachino
  • Voltage level shifter with high impedance tri-state output and method of operation
    Patent number: 6384631
    Abstract: There is disclosed a voltage level shifter that receives an input signal having a maximum Logic 1 value of VDD and produces an output signal having a maximum Logic 1 value of VDDI/O, where VDDI/O is greater than VDD.
    Type: Grant
    Filed: April 27, 2001
    Date of Patent: May 7, 2002
    Assignee: National Semiconductor Corporation
    Inventors: Joseph D. Wert, William E. Ballachino