Abstract: The present disclosure presents a circuit, a method, and a system to drive a half-bridge switch using depletion (D) mode compound semiconductor (III-V) switching transistors for a DC-DC converter using at least one driver to drive the switches of the circuit. Also included is at least one charge pump electrically connected to a gate of the transistor, to maintain a voltage that holds the transistor in an off-state. The circuit includes AC coupling capacitors to level shift a voltage and realize fast transistor switching.

Abstract: Devices and methods are described for fabricating field effect transistors (FET) using compound semiconductor front end of line (FEOL) integrated with back end of line (BEOL) technologies for applications including power management and communications. Wafer-level FEOL processing with a minimum number of thin interconnects may be used to produce multiple chiplets, which are small, high current density functional building blocks. Chiplets may have tight source/drain finger pitch, high gate width per area, and minimum lateral current flow, to reduce resistance, FEOL process complexity, and cost. Panel-level BEOL processing may serve as an inexpensive extension of FEOL processes. BEOL may form multiple interconnect layers and via bars with progressively increasing thickness and cross section area. These BEOL interconnects and via bars connect together the parallel chiplets, handle lateral flow of high current and reduce electrical and thermal resistance the FETs to increase current carrying capacity of the FETs.

Abstract: The present disclosure presents a circuit, a method, and a system to drive a half-bridge switch using depletion (D) mode compound semiconductor (III-V) switching transistors for a DC-DC converter using at least one driver to drive the switches of the circuit. Also included is at least one charge pump electrically connected to a gate of the transistor, to maintain a voltage that holds the transistor in an off-state. The circuit includes AC coupling capacitors to level shift a voltage and realize fast transistor switching.

Abstract: The present disclosure presents a circuit, a method, and a system to drive a half-bridge switch using depletion (D) mode compound semiconductor (III-V) switching transistors for a DC-DC converter using at least one driver to drive the switches of the circuit. Also included is at least one charge pump electrically connected to a gate of the transistor, to maintain a voltage that holds the transistor in an off-state. The circuit includes AC coupling capacitors to level shift a voltage and realize fast transistor switching.

Abstract: An electronic structure may include a conductive pad on a substrate, and an insulating layer on the substrate and on the conductive pad. The insulating layer may have a via therein so that a portion of the conductive pad opposite the substrate is free of the insulating layer. A conductive layer comprising copper may be on the portion of the conductive pad free of the insulating layer, on sidewalls of the via, and on surface portions of the insulating layer surrounding the via opposite the substrate and the conductive pad, and the conductive layer comprising copper may have a thickness of at least approximately 1.0 ?m. A conductive barrier layer may be on the conductive layer comprising copper, and the conductive barrier layer may include at least one of nickel, platinum, palladium, and/or combinations thereof.

Abstract: An electronic structure may include a conductive pad on a substrate, and an insulating layer on the substrate and on the conductive pad. The insulating layer may have a via therein so that a portion of the conductive pad opposite the substrate is free of the insulating layer. A conductive layer comprising copper may be on the portion of the conductive pad free of the insulating layer, on sidewalls of the via, and on surface portions of the insulating layer surrounding the via opposite the substrate and the conductive pad, and the conductive layer comprising copper may have a thickness of at least approximately 1.0 ?m. A conductive barrier layer may be on the conductive layer comprising copper, and the conductive barrier layer may include at least one of nickel, platinum, palladium, and/or combinations thereof.

Abstract: Methods of forming an electronic structure may include forming a seed layer on an electronic substrate, and forming a conductive shunt layer on portions of the seed layer wherein portions of the seed layer are free of the conductive shunt layer. A conductive barrier layer may be formed on the conductive shunt layer opposite the seed layer wherein the conductive shunt layer comprises a first material and wherein the barrier layer comprises a second material different than the first material. Moreover, a solder layer may be formed on the barrier layer opposite the conductive shunt layer wherein the solder layer comprises a third material different than the first and second materials. Related structures are also discussed.

Abstract: An integrated circuit device may include a substrate, a conductive pad on a surface of the substrate, and a conductive line on the surface of the substrate. Moreover, the conductive line may be connected to the conductive pad, and the conductive line may be narrow relative to the conductive pad. In addition, an insulating layer may be provided on the substrate, on the conductive line, and on edge portions of the conductive pad. The insulating layer may have a hole therein exposing a central portion of the conductive pad, and a first segment of a perimeter of the hole may substantially define an arc of a circle around the central portion of the conductive pad. A second segment of the perimeter of the hole may substantially deviate from the circle around the central portion of the conductive pad, and the second segment of the perimeter of the hole may be adjacent a connection between the conductive line and the conductive pad.

Abstract: Methods of forming an electronic structure may include forming a seed layer on an electronic substrate, and forming a conductive shunt layer on portions of the seed layer wherein portions of the seed layer are free of the conductive shunt layer. A conductive barrier layer may be formed on the conductive shunt layer opposite the seed layer wherein the conductive shunt layer comprises a first material and wherein the barrier layer comprises a second material different than the first material. Moreover, a solder layer may be formed on the barrier layer opposite the conductive shunt layer wherein the solder layer comprises a third material different than the first and second materials. Related structures are also discussed.

Abstract: Methods of forming an electronic structure may include forming a seed layer on an electronic substrate, and forming a conductive shunt layer on portions of the seed layer wherein portions of the seed layer are free of the conductive shunt layer. A conductive barrier layer may be formed on the conductive shunt layer opposite the seed layer wherein the conductive shunt layer comprises a first material and wherein the barrier layer comprises a second material different than the first material. Moreover, a solder layer may be formed on the barrier layer opposite the conductive shunt layer wherein the solder layer comprises a third material different than the first and second materials. Related structures are also discussed.

Abstract: Methods of forming an electronic structure may include forming a seed layer on an electronic substrate, and forming a conductive shunt layer on portions of the seed layer wherein portions of the seed layer are free of the conductive shunt layer. A conductive barrier layer may be formed on the conductive shunt layer opposite the seed layer wherein the conductive shunt layer comprises a first material and wherein the barrier layer comprises a second material different than the first material. Moreover, a solder layer may be formed on the barrier layer opposite the conductive shunt layer wherein the solder layer comprises a third material different than the first and second materials. Related structures are also discussed.

Abstract: An array of in-phase current loops are disposed adjacent to one another to define a surface and to define a virtual current loop at a periphery of the surface that produces a same direction virtual current while current in adjacent portions of adjacent current loops flows in opposite directions, to thereby wirelessly project power from the surface. It has been found according to the invention that the array of in-phase current loops that are disposed adjacent to one another to define a surface and to define a virtual current loop at a periphery of the surface that produces a same direction virtual current while current in adjacent portions of adjacent current loops flows in opposite directions, can provide acceptable power to RFID tags, while reducing the risk of violating regulatory constraints. A plurality of arrays of in-phase current loops also may be provided. The multiple arrays of in-phase current loops are disposed adjacent to one another to define a surface.

Abstract: An array of in-phase current loops are disposed adjacent to one another to define a surface and to define a virtual current loop at a periphery of the surface that produces a same direction virtual current while current in adjacent portions of adjacent current loops flows in opposite directions, to thereby wirelessly project power from the surface. It has been found according to the invention that the array of in-phase current loops that are disposed adjacent to one another to define a surface and to define a virtual current loop at a periphery of the surface that produces a same direction virtual current while current in adjacent portions of adjacent current loops flows in opposite directions, can provide acceptable power to RFID tags, while reducing the risk of violating regulatory constraints. A plurality of arrays of in-phase current loops also may be provided. The multiple arrays of in-phase current loops are disposed adjacent to one another to define a surface.