Abstract: Systems and methods are provided for reducing a set of data points into a subset of best fit data points. According to one aspect, a method of adjusting a series of N data points into best fit data points for a set of sample data points that form a data source is provided. According to this method, M segments are identified, wherein M equals N?1. Each segment has endpoints defined by adjacent subset data points. An iterative process is performed that includes determining a linear interpolation error for each of the M segments, selecting a target segment (STARGET) from the segments, and reducing the interpolation error for STARGET by moving one endpoint of STARGET by an increment corresponding to at least one sample data point in the series of sample data points to shorten STARGET. Other methods and systems are provided herein.

Abstract: A test circuit and method for measuring power supply integrity is provided. The circuit may be incorporated on-chip and is small enough to be integrated many times across the surface of the die for measuring integrity parameters at several locations on the chip. The circuit instantaneously measures, e.g., the rail voltage of a power supply, which may be fluctuating at the time of measurement. In addition, the circuit isolates itself from all chip power rails for the duration of the measurement, thereby eliminating any influence of external noise on the measurement. A storage capacitor is charged up to full power rail voltage for powering up a comparator. Then, the comparator is isolated from the power rails and the measurements are taken. Based upon the measurements, certain power supply integrity parameters are quantified including ground bounce and power droop.

Abstract: A test circuit and method for measuring power supply integrity is provided. The circuit may be incorporated on-chip and is small enough to be integrated many times across the surface of the die for measuring integrity parameters at several locations on the chip. The circuit instantaneously measures, e.g., the rail voltage of a power supply, which may be fluctuating at the time of measurement. In addition, the circuit isolates itself from all chip power rails for the duration of the measurement, thereby eliminating any influence of external noise on the measurement. A storage capacitor is charged up to full power rail voltage for powering up a comparator. Then, the comparator is isolated from the power rails and the measurements are taken. Based upon the measurements, certain power supply integrity parameters are quantified including ground bounce and power droop.

Abstract: An integrated circuit testing apparatus having at least two of a test circuit producing a signal for determining at least one of an operating reference signal and a substrate coupling effect on a plurality of components within the integrated circuit; a test circuit producing a signal for determining at least one of a cross-talk effect on the plurality of components and the accuracy of an interconnect capacitance extraction value; a test circuit producing a signal for determining at least one of an effect of system noise on the operational speed of the plurality of components and a maximum degradation expected for a logic path between the plurality of components; and a test circuit producing a signal for determining an effect of power supply noise on a signal propagation delay within the plurality of components.

Abstract: The invention relates to a method for measuring the effects of on-chin noise on signal propagation comprising measuring an inactive operating frequency of a first test circuit having a first plurality of elements connected by a first plurality of traces, measuring an inactive operating frequency of a second test circuit having a second plurality of elements connected by a second plurality of traces, measuring an inactive operating frequency of a third test circuit having a third plurality of elements connected by a third plurality of traces, and measuring an inactive operating frequency of a fourth test circuit having a fourth plurality of elements connected by a fourth plurality of traces, wherein the inactive operating frequencies of the first second, third, and fourth test circuits represent one or more effects of on-chin noise on signal propagation.

Abstract: The invention relates to an apparatus for dynamically testing an integrated circuit having a core logic area. The apparatus comprises a first test circuit having a first plurality of elements connected by a first plurality of traces wherein the first test circuit mimics a data path within the integrated circuit, a second test circuit having a second plurality of elements connected by a second plurality of traces wherein the second plurality of traces are routed within the core logic area, a third test circuit having a third plurality of elements connected by a third plurality of traces wherein the third plurality of elements are randomly located within the core logic area, and a fourth test circuit having a fourth plurality of elements connected by a fourth plurality of traces wherein the fourth test circuit mimics a data path within the integrated circuit.

Abstract: The invention relates to an integrated circuit testing apparatus having a first test circuit producing a signal for determining at least one of an operating reference signal and a substrate coupling effect on a plurality of components within the integrated circuit; a second test circuit producing a signal for determining at least one of a cross-talk effect on the plurality of components and the accuracy of an interconnect capacitance extraction value; a third test circuit producing a signal for determining at least one of an effect of system noise on the operational speed of the plurality of components and a maximum degradation expected for a logic path between the plurality of components; and a fourth test circuit producing a signal for determining an effect of power supply noise on a signal propagation delay within the plurality of components. Methods of operating such a testing apparatus are also disclosed.

Abstract: The invention relates to an integrated circuit, comprising a core logic area having a plurality of components therein, a first test circuit constructed to mimic a data path within the core logic area, a second test circuit constructed with a plurality of traces routed within the core logic area, a third test circuit constructed with a plurality of elements randomly placed within the core logic area, and a fourth test circuit constructed to mimic a data path within the core logic area, the fourth test circuit sharing a power source with at least one of the plurality of components within the core logic area. Each of the test circuits is operable to produce one or more signals for analyzing the effects of on-chip noise on signal propagation.

Abstract: The invention relates to a method for dynamically testing the effects of signal noise and cross-talk on an integrated circuit having a core logic area. The method comprises measuring an inactive operating frequency for each of the plurality of test circuits, measuring an active operating frequency for each of a plurality of test circuits, and analyzing the plurality of inactive operating frequencies and the plurality of active operating frequencies to determine the effects of signal noise and cross-talk on the integrated circuit.

Abstract: The invention relates to a combination for determining the effects of signal noise and cross-talk on on-chip propagation, comprising an integrated circuit, and a testing system having a signal generator, a plurality of ring oscillators responsive to the signal generator and a signal analyzer responsive to the plurality of ring oscillators for dynamically measuring the effects of noise and cross-talk on the integrated circuit. The plurality of ring oscillators includes a first ring oscillator constructed to mimic a data path within the integrated circuit, a second ring oscillator constructed with traces routed within the core logic area, a third ring oscillator randomly placed within the core logic area, and a fourth ring oscillator constructed to mimic a data path within the integrated circuit, the fourth ring oscillator sharing a power source with at least one component of the plurality of components within the core logic area.

Abstract: An integrated circuit testing apparatus having at least two of a first test circuit producing a signal for determining at least one of an operating reference signal and a substrate coupling effect on a plurality of components within the integrated circuit; a second test circuit producing a signal for determining at least one of a cross-talk effect on the plurality of components and the accuracy of an interconnect capacitance extraction value; a third test circuit producing a signal for determining at least one of an effect of system noise on the operational speed of the plurality of components and a maximum degradation expected for a logic path between the plurality of components; and a fourth test circuit producing a signal for determining an effect of power supply noise on a signal propagation delay within the plurality of components.

Abstract: The invention relates to an integrated circuit testing apparatus having a first test circuit producing a signal for determining at least one of an operating reference signal and a substrate coupling effect on a plurality of components within the integrated circuit; a second test circuit producing a signal for determining at least one of a cross-talk effect on the plurality of components and the accuracy of an interconnect capacitance extraction value; a third test circuit producing a signal for determining at least one of an effect of system noise on the operational speed of the plurality of components and a maximum degradation expected for a logic path between the plurality of components; and a fourth test circuit producing a signal for determining an effect of power supply noise on a signal propagation delay within the plurality of components. Methods of operating such a testing apparatus are also disclosed.

Abstract: The invention relates to an integrated circuit testing apparatus having a first test circuit producing a signal for determining at least one of an operating reference signal and a substrate coupling effect on a plurality of components within the integrated circuit; a second test circuit producing a signal for determining at least one of a cross-talk effect on the plurality of components and the accuracy of an interconnect capacitance extraction value; a third test circuit producing a signal for determining at least one of an effect of system noise on the operational speed of the plurality of components and a maximum degradation expected for a logic path between the plurality of components; and a fourth test circuit producing a signal for determining an effect of power supply noise on a signal propagation delay within the plurality of components. Methods of operating such a testing apparatus are also disclosed.

Abstract: The invention relates to an integrated circuit testing apparatus having a first test circuit producing a signal for determining at least one of an operating reference signal and a substrate coupling effect on a plurality of components within the integrated circuit; a second test circuit producing a signal for determining at least one of a cross-talk effect on the plurality of components and the accuracy of an interconnect capacitance extraction value; a third test circuit producing a signal for determining at least one of an effect of system noise on the operational speed of the plurality of components and a maximum degradation expected for a logic path between the plurality of components; and a fourth test circuit producing a signal for determining an effect of power supply noise on a signal propagation delay within the plurality of components. Methods of operating such a testing apparatus are also disclosed.

Abstract: The invention relates to an integrated circuit testing apparatus having a first test circuit producing a signal for determining at least one of an operating reference signal and a substrate coupling effect on a plurality of components within the integrated circuit; a second test circuit producing a signal for determining at least one of a cross-talk effect on the plurality of components and the accuracy of an interconnect capacitance extraction value; a third test circuit producing a signal for determining at least one of an effect of system noise on the operational speed of the plurality of components and a maximum degradation expected for a logic path between the plurality of components; and a fourth test circuit producing a signal for determining an effect of power supply noise on a signal propagation delay within the plurality of components. Methods of operating such a testing apparatus are also disclosed.

Abstract: The invention relates to an integrated circuit testing apparatus having a first test circuit producing a signal for determining at least one of an operating reference signal and a substrate coupling effect on a plurality of components within the integrated circuit; a second test circuit producing a signal for determining at least one of a cross-talk effect on the plurality of components and the accuracy of an interconnect capacitance extraction value; a third test circuit producing a signal for determining at least one of an effect of system noise on the operational speed of the plurality of components and a maximum degradation expected for a logic path between the plurality of components; and a fourth test circuit producing a signal for determining an effect of power supply noise on a signal propagation delay within the plurality of components. Methods of operating such a testing apparatus are also disclosed.

Abstract: An exemplary method of creating a cell library suitably includes, for each of a plurality of cells, determining a status of the cell and indicating the status with an electronic record. The electronic record associated with each of the cells is validated, and the validated cells are compiled to create the cell library. Testing may include manual testing of datasheets and the like, as well as electronic test of the cell design. According to yet another aspect of the invention, a method of creating a cell library suitably includes testing one or more cells to determine a status of the cell and to record the status in a data file associated with the cell, and compiling said plurality of cells to create the cell library, wherein the compiling step includes verifying the data file for each of the plurality of cells and including in the cell library only those cells having an associated data file that is free of error indicia.

Abstract: The invention relates to an integrated circuit testing apparatus having a first test circuit producing a signal for determining at least one of an operating reference signal and a substrate coupling effect on a plurality of components within the integrated circuit; a second test circuit producing a signal for determining at least one of a cross-talk effect on the plurality of components and the accuracy of an interconnect capacitance extraction value; a third test circuit producing a signal for determining at least one of an effect of system noise on the operational speed of the plurality of components and a maximum degradation expected for a logic path between the plurality of components; and a fourth test circuit producing a signal for determining an effect of power supply noise on a signal propagation delay within the plurality of components. Methods of operating such a testing apparatus are also disclosed.

Abstract: Systems and methods are provided for reducing a set of data points into a subset of best fit data points. According to one aspect, a method of adjusting a series of N data points into best fit data points for a set of sample data points that form a data source is provided. According to this method, M segments are identified, wherein M equals N−1. Each segment has endpoints defined by adjacent subset data points. An iterative process is performed that includes determining a linear interpolation error for each of the M segments, selecting a target segment (STARGET) from the segments, and reducing the interpolation error for STARGET by moving one endpoint of STARGET by an increment corresponding to at least one sample data point in the series of sample data points to shorten STARGET. Other methods and systems are provided herein.

Abstract: A test circuit and method for measuring power supply integrity is provided. The circuit may be incorporated on-chip and is small enough to be integrated many times across the surface of the die for measuring integrity parameters at several locations on the chip. The circuit instantaneously measures, e.g., the rail voltage of a power supply, which may be fluctuating at the time of measurement. In addition, the circuit isolates itself from all chip power rails for the duration of the measurement, thereby eliminating any influence of external noise on the measurement. A storage capacitor is charged up to full power rail voltage for powering up a comparator. Then, the comparator is isolated from the power rails and the measurements are taken. Based upon the measurements, certain power supply integrity parameters are quantified including ground bounce and power droop.