Abstract: A method for dynamic focus of received energy, in a vibratory energy imaging system, into a beam in which contribution from transducers in an array of N such transducers, are progressively enabled to contribute to beam focussing dependent upon distance between a particular j-th transducer (where 1.ltoreq.j.ltoreq.N) is responsive to the depth, or range R, of the focal point at any instant of time; the initial steering angle .theta., with respect to the array normal, is used in conjunction with a range clock, to determine the time when each off-normal transducer channel is enabled to add to the beam (dynamic apodization) and to finely adjust the channel time delay to properly focus the beam after the enablement of the channel.

Abstract: Apparatus for testing data conversion/transfer functions in each of a plurality N of channels of a vibratory energy imaging system includes a multiplexer for providing, to an addressable memory having a plurality of L=2.sup.M locations in each of which a data word of B bits can be stored, a selected one of an input data word and a test data word, each of which can address one of the L locations of the memory means. The address multiplexer facilitates retrieval from memory of a B-bit data word having a value selected to implement a selected function for that channel, so that comparision of data from the selected test address with the data which has been sent to that location for storage, will indicate if proper data is stored for carrying out the designated function.

Abstract: A method for correcting data conversion/transfer errors in each of a plurality N of channels of a vibratory energy imaging system, by: providing an addressable memory having a plurality L=2.sup.M locations, each for storage of a data word of B bits; then storing in each of the L locations of the memory means a B-bit data word having a value selected to cause the output-to-input transfer function for that channel to assume a desired relationship, with respect to a standard transfer measure; and selecting that one of the L data word locations, responsive to that actual one of an M-bit data word output from a channel ADC or from a data bus, responsive to a test signal, in which to place corresponding data.

Abstract: Apparatus for providing a desired output signal as a function of a single-valued input signal in an electronic system, includes: an addressable memory, having a plurality L locations, each for storage of a data word of B bits; a circuit for storing in each of the L locations of the memory means a B-bit data word having a value selected to provide a particular output value; and circuitry for converting a present single-valued increment of input signal to a unique address, within the range of allowable locations of the memory, to cause each increment of input signal to select the associated one of the L data word locations, from which to output corresponding data.

Abstract: The input signals to the weighted summation circuitry are weighted by respective weighting factors on a digit-sliced basis. Each of the weighting factors is expressed as a respective plurality of portions of different weighting significance, the portions being R in number. The portions of the weighting factors expressed as digits that have the same weighting significance constitute a rank of values. These ranks of values are normalized by dividing each of them by its respective weighting significance. R ranks of capacitors are connected in R respective networks that sum the input signals, as weighted respectively by each of the ranks of normalized values, to get normalized respective partial summation results. To generate a final weighted summation result, means are provided to sum the respective partial summation results provided from the R respective networks, after the respective partial summation results have been weighted by their corresponding weighting significances to remove normalization.

Abstract: The capacitances of a pair of capacitors associated with a neural net is carried out in a complementary way, so the sum of the capacitances remains equal to a constant, C.sub.k. Each of a set of component capacitors with capacitances related in accordance with powers of two is selected to be a component of one or the other of the pair of capacitors, the selecting being done by field effect transistors (FETs) operated as transmission gates. The gate signals for the FETs are respective ones of the bits in a binary number stored in a word storage element of a semiconductor memory.

Abstract: A method for generating a stream of digital data words, each representing an analog signal amplitude from a beam of vibratory energy received by a plurality N of transducers each associated with one of a like number of separate channels of a phased array, uses the steps of: sampling, after a delay of a multiple number of cycles at a fixed frequency F, an analog input signal in each channel at a fixed frequency F for conversion to a digital data word at each sample; then demodulating the digital data word stream in each channel to baseband and reducing the data word rate by a factor D; and phase-rotating the baseband data stream of each channel by a phase difference .DELTA..phi. determined by the focal range R and steering angle .theta. to obtain, along both the sampling delay, a different channel time delay t.sub.d,j, for each j-th channel, where 1.ltoreq.j.ltoreq.N, necessary to steer and focus the beam to a desired angle/range combination.

Abstract: The invention relates to holography and more particularly to an electronic holographic apparatus whose electrical output represents the magnitude and phase of coherent light reflected from a three-dimensional object and distributed over the aperture of the apparatus. The apparatus provides a coherent beam which illuminates the object to create a speckle pattern in an aperture bounding an optical sensing arrangement. A reference beam derived from the same source as the illuminating beam illuminates the sensing aperture directly and creates fringes in the speckle pattern. The optical sensing arrangement consists of a charge injection device (CID) camera with plural optical detectors arranged in relation to the speckle pattern to sense the magnitude and spatial phase of each speckle (on the average).

Abstract: Apparatus for the cross-correlation of two complex sampled digital data signals X and Y uses a first N-stage CORDIC rotator of pipeline sequential form for rotating each of the real and imaginary data portions of the first (X) complex sampled signal sequentially through a summation of angles .theta.=.xi..sub.i .alpha..sub.i where .xi..sub.i =+1 or -1, .alpha..sub.1 =90.degree. and .alpha..sub.n-2 =tan.sup.-1 (2.sup.-n) for n=0, 1, 2, 3, . . . N-2) until X.sub.Im is approximately zero and a substantially zero phase angle is reached. The sign from each i-th stage, of this first pipeline is also utilized to determine the sign of rotation in each like-positioned i-th stage of a plurality M of additional CORDIC pipeline rotators, where M is the total number of time delays at which the cross-correlation function is evaluated.

Abstract: A high resolution analog-to-digital (A/D) converter (14) and a pipelined A/D converter are used in a single system so that unknown offset and gain errors of the pipe-lined A/D converter are determined and corrected. Each stage of the pipelined A/D converter includes a flash A/D converter (16), a corresponding digital-to-analog (D/A) converter (18), and a differential amplifier (20) so that, in each stage the output voltage of the D/A converter is subtracted from a sample of the analog input voltage, to constitute the input signal for the next stage. The flash A/D converter of each stage addresses digital words in memory (22) which, when summed by an adder chain (24), constitute the output signal of the system. The flash A/D converter output signals are also supplied to corresponding stages of a shift register (28 or 28') which accumulates the memory address bits.

Abstract: A CORDIC (COordinate Rotation DIgital Computer) subsystem for multiplication of two complex digital numbers B and C, where one number is the sum of real and imaginary data portions, expressed in rectangular form (say C.sub.r or C.sub.I), and the other number can be expressed in the rectangular form or can be represented by magnitude data, expressed in polar form (say, .vertline.B.vertline., .phi.). An N-stage CORDIC portion of either recursive or pipeline sequential form, but devoid of multipliers, is used to rotate the I and Q terms of the first number through a phase angle .phi. of the polar-form multiplier number of the equivalent, taken from the rectangular form. The final computed data are the real and imaginary parts of the product.

Abstract: A two-dimensional ultrasonic phase array is a rectilinear approximation to a circular aperture and is formed by a plurality of transducers, arranged substantially symmetrical about both a first (X) axis and a second (Y) axis and in a plurality of subarrays, each extended in a first direction (i.e. parallel to the scan axis X) for the length of a plurality of transducers determined for that subarray, but having a width of a single transducer extending in a second, orthogonal (the out-of-scan-plane, or Y) direction to facilitate dynamic focussing and/or dynamic apodization. Each subarray transducer is formed of a plurality of sheets (part of a 2-2 ceramic composite) all electrically connected in parallel by a transducer electrode applied to juxtaposed first ends of all the sheets in each transducer, while a common electrode connects the remaining ends of all sheets in each single X-coordinate line of the array.

Abstract: A method for generating an output stream of digital data words, with each data word representing the amplitude of an analog signal at one of a multiplicity F samples each second and with substantially equally spaced time intervals T therebetween, is obtained from a digital baseband demodulation system used for array beam forming. A data stream, formed of interleaved ADC output digital data words acquired from a set of converters, is at a rate of F total samples/second. Subsequent digital demodulation, filtration, and decimation provides digital output signals which need less delay resolution prior to the formation of coherent sum signals, thereby reducing overall channel memory requirements. The output baseband data stream has enhanced dynamic range, thereby reducing the ADC bit density requirements.

Abstract: A CMOS programmable logic array includes a logical AND plane receiving a first group of input logic signals for forming a second group of logic minterms, and a logical OR plane receiving the logic minterms for forming a third group of output logic signals. Each type of logical plane contains a plurality of logic gates. Each plane type can be formed from the other plane type by the addition of a logic inverter to each input, and output of, that other-type plane. Interconnections determine the combination of input signals used to define the logic equation of the signal at the output of each logic gate of each plane. Static latches are used to retain the states of input and minterm logic signals. Logic planes and latches can be operated responsive to a two-phase clock signal.

Abstract: A first video signal is provided comprising a plurality of lines of a luminance signal, a first color signal and a second color signal, each of the lines having a duration of a first predetermined time. Each of the nonoverlapping pairs of successive lines of the luminance signal are summed and differenced to provide a luminance sum signal and a luminance difference signal. Each of the nonoverlapping pairs of successive lines of the first color signal and also of the second color signal are summed to provide a first color sum signal and a second color sum signal. The luminance difference signal, the first color sum signal and the second color sum signal are bandwidth limited in relation to the luminance sum signal. Corresponding lines of these signals are time compressed to the same bandwidth and then time multiplexed to form a corresponding line of a first compound signal, each line of which has a duration of the aforementioned predetermined time, and alternate lines of which have zero amplitude.

Abstract: A D-type latch circuit employing only six insulated-gate field-effect transistors and four diodes includes three CMOS inverters, the first and third of which are modified inverters capable of being selectively enabled or disabled depending upon the sense of the supply voltage polarity applied thereto. To accomplish this, each of the first and third inverters includes a pair of isolation diodes. Voltage supply nodes of the second inverter are connected to latch voltage supply nodes for continuously enabling the second inverter.

Abstract: A memory cell of the general type employing one pair of IGFETs defining data nodes and cross-coupled in a latch circuit configuration for storing data, and another pair of IGFETs serving as transmission gates to selectively couple data into or out of the cell. A circuit technique provides fast writing speed by avoiding the use of load resistors in either the charge or discharge paths for the data nodes and yet ensures that the data nodes are pulled either fully to logic high or fully to logic low, as the case may be, without limitation by threshold voltage offset between the gate and source terminals of the IGFETs serving as transmission gates. High impedance leakage current discharge resistances are included, and serve only the function of discharging leakage at the nodes to maintain memory. In the disposed circuit configurations, the latch IGFETs are of opposite channel conductivity type compared to the gating IGFETs.

Abstract: A five-transistor CMOS static random-access memory cell which does not require a voltage on the address line higher than the supply voltage to effect writing, and so may be fabricated employing CMOS technology on a bulk single-crystal semiconductor substrate. The cell includes a latch comprising a complementary pair of IGFETs for actively storing one binary logic state. For storing the other binary logic state, there is only a single pull-up transistor connected to one data node and a high-impedance leakage current discharge path for the other data node. The cell also includes a pair of input/output gating transistors connected to the data nodes and operating in push-pull. Various forms of high impedance leakage current discharge path are disclosed, none of which require any increase in chip area.

Abstract: A five-transistor CMOS static latch cell useful in static flip-flop applications comprises, in one embodiment, an inverting latch cell having a data input node, a data storage node, a complementary data output node, a clock input node for selectively enabling or not enabling the cell, and a pair of voltage supply nodes. An essentially standard CMOS inverter has an output connected to the complementary data output node. The inverter includes a complementary pair of IGFETs i.e., an N-channel IGFET and a P-channel IGFET. The channel of the N-channel inverter IGFET selectively electrically connects the complementary data output node to ground. The channel of the P-channel inverter IGFET selectively electrically connects the complementary data output node to the voltage supply node. The inverter transistor gate electrodes are connected to the data storage node.

Abstract: An R/S latch circuit employing four IGFETs, one pair of P-channel IGFETs, and another pair of N-channel IGFETs. The P-channel IGFETs have channels respectively connecting Q and Q data output nodes to +V.sub.DD, and gates cross-connected to the opposite data output nodes. The N-channel IGFETs have channels respectively connecting the Q and Q data output nodes to ground, and have gates which respectively comprise the Reset (R) and Set (S) data inputs. A pair of high impedance leakage current paths may also be provided respectively electrically connecting the Q and Q data output nodes to ground. Particular integrated circuit R/S latch structures are disclosed.