Abstract: An IC generally comprises enable pin, ground pin, input pin, output pin, load switch, control circuitry, and level shifter. Load switch is coupled between the input pin and output pin and receives a negative voltage through the input pin. The control circuitry is coupled to the enable pin, the ground pin, and the load switch and controls the load switch and uses ground pin as positive supply rail and input pin as an internal ground. Voltage applied to the input terminal is negative, enabling pulling of the gate of a transistor of a level shifter to ground turns transistor as “on,” enabling a negative output signal to be provided through output pin VOUT. Therefore, the output signal (at output pin VOUT) can be ground (applied to the ground pin GND) when the transistor is “off” and can be the negative voltage (applied to the input pin VIN) when transistor is “on.

Abstract: An IC generally comprises enable pin, ground pin, input pin, output pin, load switch, control circuitry, and level shifter. Load switch is coupled between input pin and output pin and receives a negative voltage through the input pin. The control circuitry is coupled to the enable pin, the ground pin, and the load switch and controls the load switch and uses ground pin as positive supply rail and input pin as an internal ground. Voltage applied to the input terminal is negative, enabling pulling of the gate of a transistor of a level shifter to ground turns transistor as “on,” enabling a negative output signal to be provided through output pin VOUT. Therefore, the output signal (at output pin VOUT) can be ground (applied to the ground pin GND) when the transistor is “off” and can be the negative voltage (applied to the input pin VIN) when transistor is “on.

Abstract: Anti-lock and intelligent braking systems have become ubiquitous in modern vehicles, which employ wheel speed sensors or WSSs. These WSSs generally uses current-domain signals (transmitted through power wires) to reduce the size of the vehicle's wiring harness, but because a vehicle is an inherently noisy environment, mixed signal circuit or MSC (used to decode these signals for a microcontroller) should be able to filter out or compensate for noise. However, traditional MSCs have been plagued with problems, partly due to errors in time base measurement due to noise (as well as other factors). Here, an MSC is provided that accurately calculates a wheel speed pulse width (which is used for time base measurements) by observing the wheel speed pulse as it passes through several thresholds.

Abstract: Anti-lock and intelligent braking systems have become ubiquitous in modern vehicles, which employ wheel speed sensors or WSSs. These WSSs generally uses current-domain signals (transmitted through power wires) to reduce the size of the vehicle's wiring harness, but because a vehicle is an inherently noisy environment, mixed signal circuit or MSC (used to decode these signals for a microcontroller) should be able to filter out or compensate for noise. However, traditional MSCs have been plagued with problems, partly due to errors in time base measurement due to noise (as well as other factors). Here, an MSC is provided that accurately calculates a wheel speed pulse width (which is used for time base measurements) by observing the wheel speed pulse as it passes through several thresholds.

Abstract: A deglitch circuit utilizes a first flip-flop coupled to the input signal and a second flip-flop coupled to the output of a circuit with feedback from the output to gates to control first and second inputs to the first flip-flop. In an alternative arrangement, a counter is provided between the output of the first flip-flop and the input to the second flip-flop in order to provide flexibility and the possibility of a longer delay for the circuit.

Abstract: A method and system for testing a device that includes both a digital and analog portion. The digital portion includes a plurality of latch devices, and the analog portion includes a plurality of memory cells and a plurality of selector devices. A selector input controls each of the plurality of selector devices, which is electrically coupled to a respective one of the memory cells, and is indirectly coupled to one of the plurality of latch devices. A load clock loads a pattern into the plurality of latch devices. A derivative of the pattern is received by the plurality of selectors and returned to the plurality of latch devices with the assertion of the selector input. A system clock loads the derivative of the pattern into the plurality of latch devices.

Abstract: A reverse battery protection circuits that provides an integrated reverse battery condition solution for protection of external NMOS switches during the reverse battery condition is disclosed herein. This reverse battery protection circuit minimizes power consumption during a reverse battery event wherein there is no need for mechanical adjustments such as heat sinking and clamping to extract the heat away from the silicon and not destroy the device. Specifically, the reverse battery protection circuit includes a push-pull gate drive circuit coupled between the first and second power supply rail. A protection subcircuit portion connects between a first output node and the second power supply rail to turn the external FET ‘on’ during the reverse battery condition. In particular, the protection subcircuit portion connects to the external FET device and includes a p-channel device connected between a second output node that biases the external FET device and a first diode.

Abstract: A system and method are provided to regulate resistance in a discontinuous time hot-wire anemometer. The solution removes supply voltage dependency on the mass airflow output signal. Operating the hot-wire anemometer using discontinuous time regulation offers lower system power, but introduces an inverse supply dependent term in the associated transfer function. This effect is removed by multiplying the output signal via a supply dependent signal.

Abstract: System for providing a switched regulator with an adjustable operating frequency range. A preferred embodiment comprises a voltage supply and a load, a switch and filter block (SFB) (such as the SFB 510), a comparator (such as the comparator 520), and a fixed off time logic (FOTL) (such as the FOTL 525). The comparator compares an output voltage with a reference voltage. When the output voltage is equal to or exceeds the reference voltage, the comparator asserts a value on a signal line to the FOTL. The FOTL then shuts down the SFB for a specified period of time. During the off time, the output voltage decays. After the specified period of time expires, the SFB is turned back on and the output voltage can recharge. The duration of time that the SFB remains on is a function of the supply voltage, thus permitting an adjustable operating frequency.

Abstract: In accordance with the teachings of the present invention, a system and method for regulating bridge voltage in a discrete-time hot-wire anemometer is provided. In a particular embodiment, the hot-wire anemometer includes a bridge circuit including a hot-wire resistor, first and second input terminals, and first and second output terminals, the hot-wire resistor having a resistance dependent at least in part on an airflow past the hot-wire resistor. The hot-wire anemometer further includes a first operational amplifier coupled to the output terminals of the bridge circuit, the first operational amplifier operable to generate an output signal in response to a voltage differential across the first and second output terminals of the bridge circuit, and a second operational amplifier operable to generate an output signal in response to the output signal of the first operational amplifier and to a discontinuous time control signal.

Abstract: The present invention provides a system (200) for controlling drive signal timing parameters of an output driver circuit (206). The present invention defines a driver circuit having an output interface (204), and a first transistor (222) coupled to a first voltage supply (230), a first control signal (232), and a first node (220). The circuit also has a first resistive element, coupled between the first node and a second node (234). A second resistive element (228) is coupled to ground. A second transistor (224) is coupled to the second node, to a second control signal (236), and the second resistive element. The circuit has a third transistor (244), coupled to the first and second nodes, and to a third node (240). A third resistive element (242) is coupled between the third node and the output interface. A fourth transistor (238) is coupled to the first and third nodes, and to the output interface.

Abstract: Disclosed are devices and associated methods for manufacturing an EEPROM memory cell (10) for use on a negatively biased substrate (12). The invention may be practiced using standard semiconductor processing techniques. Devices and methods are disclosed for a floating gate transistor for use as an EEPROM cell (10) including a DNwell (14) formed on a P-type substrate (12) for isolating the EEPROM cell (10) from the underlying P-type substrate (12).

Abstract: Disclosed are devices and associated methods for manufacturing an EEPROM memory cell (10) for use on a negatively biased substrate (12). The invention may be practiced using standard semiconductor processing techniques. Devices and methods are disclosed for a floating gate transistor for use as an EEPROM cell (10) including a DNwell (14) formed on a P-type substrate (12) for isolating the EEPROM cell (10) from the underlying P-type substrate (12).

Abstract: Driver circuitry (300) is disclosed, incorporating feedback circuitry (310) inter-coupled with reference circuitry (348) to equalize the voltage level of an output (328) with a reference voltage source (320) in the reference circuitry; where the driver circuitry comprises a first transistor (340) having a first terminal coupled to a voltage source (342), a second terminal coupled to an input (336), and a third terminal coupled to a resistor (344), a second transistor (338) having a first terminal coupled to ground (332), a second terminal coupled to an input (334), and a third terminal coupled to a resistor (346), a third transistor (318) having a first terminal coupled to the output, a second terminal (326) coupled jointly to the resistors, and a third terminal coupled to ground, and a resistor (330) coupling the output to a voltage source (306).

Abstract: A voltage level shifting circuit (60) and method for accomplishing a voltage level change includes a voltage level shifting circuit (65) to change an input voltage to a shifted voltage level. A second stage (67) is connected between a voltage source at the shifted voltage level (68) and the reference potential. The second stage (67) includes active devices (66,82) that are controlled by the voltage level shifting circuit (65). The second stage (67) also includes slope resistors (86,88) connected in series between the active devices (66,82) of the second stage (67).