Abstract: An interrupt control unit which couples a plurality of peripheral devices to a central processor includes a counter for outputting signals for monitoring a plurality of encoders each coupled to a number of peripheral devices, each encoder outputting the address of a requesting peripheral device when enabled. A memory unit outputs the address of the highest priority peripheral device for each output signal of the counter and a comparator compares the address of the peripheral device having the highest priority access outputted by the memory unit with the address of the previously interrupting peripheral device to determine priority access to the central processor.