Abstract: A reply decoder (30) for declaring mode 4 replies when used with a KIR cryptograph computer (25) is described including timing logic (114), memory (112) for storing mode 4 replies and logic circuitry for analyzing replies stored in the memory (112). The invention further provides logic circuitry for detecting railing (117) i.e., successive replies, for detecting garbled or overlapping replies (123), for providing a floating density value window (114, 120) for summing the replies in nonselected reply positions and for target start/stop determination (215) based on selected criteria. The invention overcomes the problem of declaring excessive mode 4 replies which over burden the subsequent reply processing in a reply processor (50).

Abstract: A decoder for separating pulse code modulated messages of the type used in ATCRBS where the messages are identified by two framing pulses separated by 20.3 us. and contain information pulses between the framing pulses separated from the framing pulses and from one another by 1.45 us. The decoder receives an input stream of pulses of uniform width from a Leading Edge Detector which has created the stream from video pulses received from the transmitter of another station. The decoder input pulse stream may contain interleaved pulses from more than one message. The decoder includes an input shift register, an analysis shift register, a plurality of buffer storage devices and additional registers to which selected pulses are fed from the input register for use in determining whether a received message is clear of interfering pulses or whether the message is potentially or actually garbled.