Abstract: A switch for routing input signals from any of N input terminals to one or more of M output terminals includes a high-speed N×M crosspoint switch array providing the necessary signal paths. Each of a set of N input drivers buffers a separate one of the input signals into the crosspoint array and each of a set of M output drivers buffers an array output signal onto a separate one of the output terminals. The crosspoint switch array is horizontally and/or vertically segmented by input and output buffers to limit the amount of the array's capacitance that each input driver must charge and discharge when the input signals change state, thereby reducing signal path delay through the crosspoint array.

Abstract: A high-speed, low distortion N×M crosspoint switch selectively routes input signals arriving at any of N input terminals to one or more of M output terminals. The crosspoint switch includes a switch cell array having N rows and M columns of switch cells. Each of N input lines convey the input signal arriving at a separate one of the N input signals to each switch cell of a corresponding array row. Each of M output lines convey output signals generated by cells of a corresponding array column to a separate switch output terminal. Each switch cell contains a CMOS tristate buffer and a memory cell for storing data controlling whether the tristate buffer is active or inactive. When a tristate buffer is active, it buffers an input signal appearing on one of the input lines to generate an output signal on one of the output lines. When inactive, a tristate buffer refrains from generating an output signal in response to its input signal.

Abstract: A switch for routing input signals from any of N input terminals to one or more of M output terminals includes a high-speed N×M crosspoint switch array providing the necessary signal paths. Each of a set of N input drivers buffers a separate one of the input signals into the crosspoint array and each of a set of M output drivers buffers an array output signal onto a separate one of the output terminals. The crosspoint switch array is horizontally and/or vertically segmented by input and output buffers to limit the amount of the array's capacitance that each input driver must charge and discharge when the input signals change state, thereby reducing signal path delay through the crosspoint array.

Abstract: A high-speed N×M crosspoint switch selectively routes input signals arriving at any of N input terminals to one or more of M output terminals through a switch cell array having N rows and M columns of switch cells, each for selectively providing a signal path between one input terminal and one output terminal. Each switch cell contains a first memory cell holding a data bit, a second memory cell holding a control bit, and a transistor for making or braking a signal path in response to the control bit. This switch cell architecture enables the crosspoint switch to operate in normal, implied disconnect and broadcast modes. In the normal mode a controller creates a routing pattern by writing data bits to the second memory cells and then signals all switch cells to transfer their data bits into the first memory cells. In the implied disconnect mode, when any cell of a column is signaled to make a path, all other cells along that column automatically break their paths.

Abstract: A novel output stage is disclosed which includes first and second output transistors for providing complementary output signals at inverting and noninverting output terminals in response to receipt of an input signal, wherein the output stage includes a single source of current and a pair of current steering transistors which are controlled by circuit means coupled between the input terminal and the control terminals of the current steering transistors to turn on the one of the current steering transistors which is coupled to the one of the inverting and noninverting output terminals which is undergoing a high voltage to low voltage transition and to turn off the other of the current steering transistors in response to the change of state of the input signal received at an input terminal.

Abstract: A novel ECL Programmable Logic Array (PLA) is provided which operates as an ECL PLA, having ECL voltage level compatible input and output leads, thereby providing a high-speed PLA. A unique programming means is provided which allows the ECL PLA to be programmed using TTL-compatible programming voltage levels, such as are provided by common and inexpensive prior art TTL PLA programmers. In another embodiment higher speed is achieved by the design of each sense amplifier using emitter function logic such that the sense transistor and load functions a cascode amplifier. In another embodiment a lower power PLA device is achieved by utilizing a switched current source pull down means for pulling down the rows of the PLA array. In another embodiment low power and user convenience is achieved by allowing each pair of output terminals to share a predefined set of product terms.

Abstract: An ECL Programmable Logic Array (PLA) having ECL voltage level compatible input and output leads, thereby providing a high-speed PLA. A unique programming means is provided which allows the ECL PLA to be programmed using TTL-compatible programming voltage levels, such as are provided by common and inexpensive prior art TTL PLA programmers. In another embodiment higher speed is achieved by the design of each sense amplifier using emitter function logic such that the sense transistor and load functions a cascode amplifier. In another embodiment a lower power PLA device is achieved by utilizing a switched current source pull down means for pulling down the rows of the PLA array. In another embodiment low power and user convenience is achieved by allowing each pair of output terminals to share a predefined set of product terms.

Abstract: An AND gate (40) includes first and second input leads (42,43) and an output lead (44). The AND gate includes a first N channel MOS ("NMOS") transistor (58) which couples the output lead to ground in response to the signal (IN1) on the first input lead and a second NMOS transistor (60) which couples the output lead to ground in response to the signal (IN2) on the second input lead. A buffer (76) having a high output impedance is coupled to the output lead and tends to maintain the output lead in a constant state. When the signal on the first input lead goes high, the first NMOS transistor turns off and a PMOS transistor (64) turns on, thereby coupling the output lead to a high voltage source for a predetermined time period. If the second NMOS transistor is off, the resulting pulse causes the AND gate output signal (Vout) to go high. The high impedance buffer maintains the output lead in the high state.

Abstract: A fall-through memory array comprising in a plurality of rows and columns a plurality of memory cells, each memory cell comprising a pair of cross-coupled transistors having three emitters, a collector and a base. Control potentials applied to a word line, coupled to each one of two of the emitters of each of the transistors, control the transfer of data bits from one row of such memory cells to another.

Abstract: A semiconductor memory device (100) utilizing a programming transistor (54) capable of switching high programming currents, and a read transistor (53) capable of sensing the state of the cell (i.e. programmed or unprogrammed). The programming transistor, utilized only when programming the cell, being rather large, is rather slow. The read transistor, utilized only when reading the cell, is constructed to be as small as possible, thereby achieving a substantially increased reading speed over prior art PROM devices which utilize a single transistor per memory cell for both programming and reading.

Abstract: A bidirectional serially controlled programmable read-only memory has a serial input/output (I/O) port and a parallel I/O port. By selecting the appropriate control inputs, the instant invention can receive serial address or data information and output data to either the parallel or serial I/O ports. In a like manner, an address at the parallel I/O port can be utilized to generate output data in either a serial or parallel form. In general, the parallel I/O port will be utilized to transfer data to and from a microprocessor, whereas the serial I/O port will be utilized to transfer data to and from an external interface. By proper utilization of the control circuits and appropriate use of the control signals, data may be read from the bidirectional PROM in parallel form from the parallel I/O port or in serial form from the serial I/O port. In addition, data may be transferred from the serial I/O port to the parallel I/O port or from the parallel I/O port to the serial I/O port.

Abstract: This disclosure is directed to a First In First Out memory which comprises a register, an input control section, a register control section, and an output control section. The imput control section allows data to be entered into the First In First Out memory while the register control section shifts the data through the memory queing up at the locations closest to the output. The output control allows data to be taken out of the FIFO at a different rate than data is entered into the memory by the input control section. The register control section monitors the succeeding location and the previous location in the register to determine when data may be shifted in the register.