Patents by Inventor William E. Rader, III

William E. Rader, III has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260095988
    Abstract: An apparatus includes a voltage detection module and a sense resistor configured to couple a low-voltage domain of the voltage detection module to a high-voltage node of an external circuit and to develop a sense current based on a voltage developed at the high-voltage node, the sense current being received at a sensing node of the voltage detection module. The voltage detection module includes a reference network configured to establish one or more threshold conditions at respective internal nodes within the voltage detection module, the one or more threshold conditions being generated based on one or more biasing circuits, and a comparison network configured to generate one or more comparison output signals based on a received current level of the sense current and the one or more threshold conditions.
    Type: Application
    Filed: September 25, 2025
    Publication date: April 2, 2026
    Applicant: Silanna Asia Pte Ltd
    Inventors: Russell Hayter, William E. Rader, III, Kenneth Leigh Boyden, Stuart B. Molin, Steven E. Rosenbaum
  • Publication number: 20260039123
    Abstract: A multi-port charger allocates a total allocated power to power delivery modules to provide power to respective sink devices at less than or equal to a total rated power capacity of the multi-port charger. Under predetermined conditions, a subsequent power allocation provided to a sink device is allowed to result in the total allocated power of the multi-port charger being greater than the total rated power capacity of the multi-port charger. After the total allocated power has been higher than the total rated power capacity for longer than a timeout time period, the total allocated power is reset to be less than or equal to the total rated power capacity of the multi-port charger.
    Type: Application
    Filed: August 2, 2024
    Publication date: February 5, 2026
    Applicant: Silanna Asia Pte Ltd
    Inventor: William E. Rader, III
  • Publication number: 20250350091
    Abstract: A pulsed laser diode driver includes an inductor having a first terminal configured to receive a first source voltage provided by a source capacitor. A bypass switch has a drain node connected to a second terminal of the inductor. A laser diode has an anode connected to the second terminal of the inductor and a cathode connected to a drain node of a pulse emission switch. The pulse emission switch and the bypass switch are configured to control a current flow through the inductor to emit a high-current pulse through the laser diode to thereby emit a light pulse corresponding to a peak current of a resonant waveform developed at the anode of the laser diode. The bypass switch is enabled during emission of the high-current pulse to modify a falling edge of the high-current pulse.
    Type: Application
    Filed: July 18, 2025
    Publication date: November 13, 2025
    Applicant: Silanna Asia Pte Ltd
    Inventors: Joseph H. Colles, Steven E. Rosenbaum, William E. Rader, III, Stuart B. Molin, Aleksandar Radic
  • Publication number: 20250174964
    Abstract: A pulsed laser diode driver includes a source capacitor having a first terminal connected to a respective first terminal of two or more inductors and a second terminal coupled to ground. First and second bypass switches each have a respective drain node connected to a respective second terminal of first and second inductors of the two or more inductors and a respective source node connected to ground. First and second laser diodes each have a respective anode connected to the respective second terminal of the first and second inductors. The bypass switches are configured to control a current flow through the first and second inductors to produce high-current pulses through the laser diodes, each high-current pulse corresponding to a peak current of a resonant waveform developed at the anode of the respective laser diode.
    Type: Application
    Filed: January 30, 2025
    Publication date: May 29, 2025
    Applicant: Silanna Asia Pte Ltd
    Inventors: Steven E. Rosenbaum, William E. Rader, III, Joseph H. Colles, Stuart B. Molin, Aleksandar Radic
  • Publication number: 20240372458
    Abstract: A power converter includes an AC/DC converter to generate a DC output voltage based on an AC input voltage. A multi-port DC output circuit receives the DC output voltage and provides respective DC output voltages to a first DC output port and a second DC output port. The multi-port DC output circuit includes a first intermediate rail voltage switch, a second intermediate rail voltage switch, and multiple bus switches, a body diode of the first intermediate rail voltage switch being forward biased with respect to the first secondary side output voltage, and a body diode of the second intermediate rail voltage switch being reverse biased with respect to the first secondary side output voltage. The bus switches control a routing of a first intermediate rail voltage and a second intermediate rail voltage of the multi-port DC output circuit to the first DC output port and the second DC output port.
    Type: Application
    Filed: April 30, 2024
    Publication date: November 7, 2024
    Applicant: Silanna Asia Pte Ltd
    Inventors: William E. Rader, III, Aleksandar Radic
  • Patent number: 12126341
    Abstract: A transistor is switched on and off with an on-time that is held constant and an off-time that is varied. When the off-time is detected to be less than a threshold value that is greater than a minimum off-time limit, the on-time is extended. Then the power transistor is switched on and off with the extended on-time that is held constant and the off-time that varies.
    Type: Grant
    Filed: April 17, 2023
    Date of Patent: October 22, 2024
    Assignee: Silanna Asia Pte Ltd
    Inventors: Robert Eric Fesler, William E. Rader, III, Yashovardhan R. Potlapalli
  • Publication number: 20230253956
    Abstract: A transistor is switched on and off with an on-time that is held constant and an off-time that is varied. When the off-time is detected to be less than a threshold value that is greater than a minimum off-time limit, the on-time is extended. Then the power transistor is switched on and off with the extended on-time that is held constant and the off-time that varies.
    Type: Application
    Filed: April 17, 2023
    Publication date: August 10, 2023
    Applicant: Silanna Asia Pte Ltd
    Inventors: Robert Eric Fesler, William E. Rader, III, Yashovardhan R. Potlapalli
  • Patent number: 11664785
    Abstract: A power transistor is switched on and off with an on-time that is held constant and an off-time that is varied. When the off-time is detected to be less than a threshold value that is greater than a minimum off-time limit, the on-time is extended. Then the power transistor is switched on and off with the extended on-time that is held constant and the off-time that varies.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: May 30, 2023
    Assignee: Silanna Asia Pte Ltd
    Inventors: Robert Eric Fesler, William E. Rader, III, Yashovardhan R. Potlapalli
  • Publication number: 20220190811
    Abstract: A power transistor is switched on and off with an on-time that is held constant and an off-time that is varied. When the off-time is detected to be less than a threshold value that is greater than a minimum off-time limit, the on-time is extended. Then the power transistor is switched on and off with the extended on-time that is held constant and the off-time that varies.
    Type: Application
    Filed: March 2, 2022
    Publication date: June 16, 2022
    Applicant: Silanna Asia Pte Ltd
    Inventors: Robert Eric Fesler, William E. Rader, III, Yashovardhan R. Potlapalli
  • Patent number: 11290090
    Abstract: A power transistor is switched on and off with an on-time that is held constant and an off-time that is varied. When the off-time is detected to be less than a threshold value that is greater than a minimum off-time limit, the on-time is extended. Then the power transistor is switched on and off with the extended on-time that is held constant and the off-time that varies.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: March 29, 2022
    Assignee: Silanna Asia Pte Ltd
    Inventors: Robert Eric Fesler, William E. Rader, III, Yashovardhan R. Potlapalli
  • Publication number: 20210257998
    Abstract: A power transistor is switched on and off with an on-time that is held constant and an off-time that is varied. When the off-time is detected to be less than a threshold value that is greater than a minimum off-time limit, the on-time is extended. Then the power transistor is switched on and off with the extended on-time that is held constant and the off-time that varies.
    Type: Application
    Filed: December 15, 2020
    Publication date: August 19, 2021
    Applicant: Silanna Asia Pte Ltd
    Inventors: Robert Eric Fesler, William E. Rader, III, Yashovardhan R. Potlapalli
  • Patent number: 6377032
    Abstract: An apparatus and method for virtual current sensing in a DC-DC switched mode power supply. In a fixed frequency implementation, when a switching phase begins, the phase node goes high when the high-side switching transistor is turned on. At this point, a first programmable current source begins charging a current sensing capacitor and the voltage across the capacitor simulates the rising slope of the voltage across a conventional current sensing resistor. Simultaneously, a ramp capacitor beginning at a reference voltage is charged by a second programmable current source. When the sum of the voltages across the two capacitors exceeds an error voltage, the phase node goes low when the drive signal to the transistor is turned off. At this point, a third programmable current source begins discharging the current sensing capacitor and the voltage across the capacitor simulates the falling slope of the current across the conventional resistor.
    Type: Grant
    Filed: July 20, 2000
    Date of Patent: April 23, 2002
    Assignee: Semtech Corporation
    Inventors: Joseph M. Andruzzi, John Fogg, William E. Rader, III