Abstract: An infrared detector system is provided for detecting infrared radiation from an infrared radiation source or a scene. The system includes a first area that is semiconductor-based and biased to produce negative luminescence, the first area including at least one semiconductor-based detector. The detector system further includes at least one additional area being semiconductor-based and biased to produce negative luminescence. A low-emissivity specular retro-reflector shield is configured to reflect infrared radiation and covers the first area and the at least one additional area. The shield defines an aperture to allow the at least one semiconductor-based detector to receive incident rays of the infrared radiation from the infrared radiation source or the scene via a low-scatter, low-emission optical system such that the radiation incident from the infrared radiation source or scene substantially fills the solid angle defined by the aperture at any point in the first area.

Abstract: A two-terminal detector has a back-to-back p/n/p SWIR/MWIR stack structure, which includes P-SWIR absorber, N-SWIR, wide bandgap bather, N-MWIR absorber, and P-MWIR layers, with contacts on the P-MWIR and P-SWIR layers. The junction between the SWIR layers and the junction between the MWIR layers are preferably passivated. The detector stack is preferably arranged such that a negative bias applied to the top of the stack reverse-biases the MWIR junction and forward-biases the SWIR junction, such that the detector collects photocurrent from MWIR radiation. A positive bias forward-biases the MWIR junction and reverse-biases the SWIR junction, such that photocurrent from SWIR radiation is collected. A larger positive bias induces electron avalanche at the SWIR junction, thereby providing detector sensitivity sufficient to provide low light level passive amplified imaging. Detector sensitivity in this mode is preferably sufficient to provide high resolution 3-D eye-safe LADAR imaging.

Abstract: An infrared detector system is provided for detecting infrared radiation from an infrared radiation source or a scene. The system includes a first area that is semiconductor-based and biased to produce negative luminescence, the first area including at least one semiconductor-based detector. The detector system further includes at least one additional area being semiconductor-based and biased to produce negative luminescence. A low-emissivity specular retro-reflector shield is configured to reflect infrared radiation and covers the first area and the at least one additional area. The shield defines an aperture to allow the at least one semiconductor-based detector to receive incident rays of the infrared radiation from the infrared radiation source or the scene via a low-scatter, low-emission optical system such that the radiation incident from the infrared radiation source or scene substantially fills the solid angle defined by the aperture at any point in the first area.

Abstract: A two-terminal detector has a back-to-back p/n/p SWIR/MWIR stack structure, which includes P-SWIR absorber, N-SWIR, wide bandgap bather, N-MWIR absorber, and P-MWIR layers, with contacts on the P-MWIR and P-SWIR layers. The junction between the SWIR layers and the junction between the MWIR layers are preferably passivated. The detector stack is preferably arranged such that a negative bias applied to the top of the stack reverse-biases the MWIR junction and forward-biases the SWIR junction, such that the detector collects photocurrent from MWIR radiation. A positive bias forward-biases the MWIR junction and reverse-biases the SWIR junction, such that photocurrent from SWIR radiation is collected. A larger positive bias induces electron avalanche at the SWIR junction, thereby providing detector sensitivity sufficient to provide low light level passive amplified imaging. Detector sensitivity in this mode is preferably sufficient to provide high resolution 3-D eye-safe LADAR imaging.

Abstract: A self-aligning hybridization method enabling small pixel pitch hybridizations with self-alignment and run-out protection. The method requires providing a first IC, the surface of which includes at least one electrical contact for connection to a mating IC, depositing an insulating layer on the IC's surface, patterning and etching the insulating layer to provide recesses in the insulating layer above each of the electrical contacts, and depositing a deformable conductive material in each of the recesses. A mating IC is provided which includes conductive pins positioned to align with the deformable conductive material in respective ones of the recesses on the first chip. The first and mating ICs are then hybridized by bringing the conductive pins into contact with the deformable conductive material in the recesses, such that the conductive material deforms and the pins make electrical contact with the first IC's electrical contacts.

Abstract: A fully depleted “diode passivation active passivation architecture” (DPAPA) produces a photodiode structure which includes a substrate, a highly-doped buffer layer of a first carrier doping type above the substrate, a low-doped or undoped semiconductor active layer of the first carrier doping type above the buffer layer, a low-doped or undoped passivation layer above the active layer, the passivation layer having a wider band gap than the active layer; and a junction layer of a carrier doping type opposite the first carrier doping type above the passivation layer such that a pn junction is formed between the junction layer and the passivation and active layers, the junction creating a depletion region which expands completely through the passivation and active layers in response to a reverse bias voltage. The fully depleted structure substantially eliminates Auger recombination, reduces dark currents and enables cryogenic level performance at high temperatures.

Abstract: An imaging array comprises a photodetector layer, a readout IC (ROIC) layer, and a charge storage capacitor layer which is distinct from the photodetector and ROIC layers; the layers are electrically interconnected to form the array. The capacitors within the charge storage capacitor layer are preferably micromachined; the charge storage capacitor layer can be an interposer layer or an outer layer.

Abstract: Lateral collection architecture for a photodetector is achieved by depositing electrically conducting SLS layers onto a planar substrate and diffusing dopants of a carrier type opposite that of the layers through the layers at selected regions to disorder the superlattice and create diode junctions oriented transversely to the naturally enhanced lateral mobility of photogenerated charge carriers within the superlattice. The diode junctions are terminated at a top surface of the photodetector within an SLS layer of wide bandgap material to minimize unwanted currents. A related architecture disorders the superlattice of topmost SLS layers by diffusing therethrough a dopant configured as a grid and penetrating to a lower SLS layer having the same carrier type as the dopant and opposite that of the topmost layers to isolate pixels within the topmost layers. Ohmic contacts may be deposited on doped regions, pixels, and substrate to provide desired external connections.

Abstract: A self-aligning hybridization method enabling small pixel pitch hybridizations with self-alignment and run-out protection. The method requires providing a first IC, the surface of which includes at least one electrical contact for connection to a mating IC, depositing an insulating layer on the IC's surface, patterning and etching the insulating layer to provide recesses in the insulating layer above each of the electrical contacts, and depositing a deformable conductive material in each of the recesses. A mating IC is provided which includes conductive pins, preferably comprising nickel, positioned to align with the deformable conductive material in respective ones of the recesses on the first chip. The first and mating ICs are then hybridized by bringing the conductive pins into contact with the deformable conductive material in the recesses, such that the conductive material deforms and the pins make electrical contact with the first IC's electrical contacts.

Abstract: A method of improving thermal cycling reliability for a hybrid circuit structure requires providing at least two circuit layers, aligning two of the circuit layers vertically such that their respective circuit elements have a precise and well-defined spatial relationship, and providing an adhesive material which wicks into a portion of the space between the aligned layers so as to mitigate damage to the structure and/or interconnections that might otherwise occur due to thermal contraction mismatch between the layers. The adhesive material is required to have an associated viscosity such that, when provided under predetermined conditions, the adhesive stops wicking before reaching, and possibly degrading the performance of, the circuit elements.

Abstract: A method of improving thermal cycling reliability for a hybrid circuit structure requires providing at least two circuit layers, aligning two of the circuit layers vertically such that their respective circuit elements have a precise and well-defined spatial relationship, and providing an adhesive material which wicks into a portion of the space between the aligned layers so as to mitigate damage to the structure and/or interconnections that might otherwise occur due to thermal contraction mismatch between the layers. The adhesive material is required to have an associated viscosity such that, when provided under predetermined conditions, the adhesive stops wicking before reaching, and possibly degrading the performance of, the circuit elements.

Abstract: Embodiments of a read-out integrated circuit (ROIC) include a plurality of unit cells. Each unit cell includes a bias subsystem, a reset switch, at least one integration capacitor, and at least one read switch. A focal plane array includes a plurality of photo detectors disposed in a grid and a ROIC. A column buffer includes a first buffer subsystem, a feedback subsystem, a first and second correlated double sampling subsystem, and a second buffer subsystem. A ROIC includes at least one integration subsystem having a transistor subsection, a poly silicon layer, and a plurality of active layer sections.

Abstract: An imaging array comprises a photodetector layer, a readout IC (ROIC) layer, and a charge storage capacitor layer which is distinct from the photodetector and ROIC layers; the layers are electrically interconnected to form the array. The capacitors within the charge storage capacitor layer are preferably micromachined; the charge storage capacitor layer can be an interposer layer or an outer layer.

Abstract: Lateral collection architecture for a photodetector is achieved by depositing electrically conducting SLS layers onto a planar substrate and diffusing dopants of a carrier type opposite that of the layers through the layers at selected regions to disorder the superlattice and create diode junctions oriented transversely to the naturally enhanced lateral mobility of photogenerated charge carriers within the superlattice. The diode junctions are terminated at a top surface of the photodetector within an SLS layer of wide bandgap material to minimize unwanted currents. A related architecture disorders the superlattice of topmost SLS layers by diffusing therethrough a dopant configured as a grid and penetrating to a lower SLS layer having the same carrier type as the dopant and opposite that of the topmost layers to isolate pixels within the topmost layers. Ohmic contacts may be deposited on doped regions, pixels, and substrate to provide desired external connections.

Abstract: Lateral collection architecture for a photodetector is achieved by depositing electrically conducting SLS layers onto a planar substrate and diffusing dopants of a carrier type opposite that of the layers through the layers at selected regions to disorder the superlattice and create diode junctions oriented transversely to the naturally enhanced lateral mobility of photogenerated charge carriers within the superlattice. The diode junctions are terminated at a top surface of the photodetector within an SLS layer of wide bandgap material to minimize unwanted currents. A related architecture disorders the superlattice of topmost SLS layers by diffusing therethrough a dopant configured as a grid and penetrating to a lower SLS layer having the same carrier type as the dopant and opposite that of the topmost layers to isolate pixels within the topmost layers. Ohmic contacts may be deposited on doped regions, pixels, and substrate to provide desired external connections.

Abstract: A graded order-sorting filter for hyperspectral imagers and methods of making the same are provided. The graded order-sorting filter includes a substrate wafer having a first side and a second side and is formed of a material that is substantially transparent to light photons. The graded order-sorting filter also includes an absorption filter deposited outwardly from the first side of the substrate wafer. The absorption filter is tapered along a taper direction and formed of a graded composition semiconductor material with a bandgap graded to decrease outwardly from the substrate wafer and/or graded along the taper direction. The graded composition semiconductor material is substantially transparent to the light photons for photon energies substantially less than the bandgap. The above filter can also be aligned to a two-dimensional array of pixels to form a hyperspectral imager.

Abstract: Lateral collection architecture for a photodetector is achieved by depositing electrically conducting SLS layers onto a planar substrate and diffusing dopants of a carrier type opposite that of the layers through the layers at selected regions to disorder the superlattice and create diode junctions oriented transversely to the naturally enhanced lateral mobility of photogenerated charge carriers within the superlattice. The diode junctions are terminated at a top surface of the photodetector within an SLS layer of wide bandgap material to minimize unwanted currents. A related architecture disorders the superlattice of topmost SLS layers by diffusing therethrough a dopant configured as a grid and penetrating to a lower SLS layer having the same carrier type as the dopant and opposite that of the topmost layers to isolate pixels within the topmost layers. Ohmic contacts may be deposited on doped regions, pixels, and substrate to provide desired external connections.

Abstract: A graded order-sorting filter for hyperspectral imagers and methods of making the same are provided. The graded order-sorting filter includes a substrate wafer having a first side and a second side and is formed of a material that is substantially transparent to light photons. The graded order-sorting filter also includes an absorption filter deposited outwardly from the first side of the substrate wafer. The absorption filter is tapered along a taper direction and formed of a graded composition semiconductor material with a bandgap graded to decrease outwardly from the substrate wafer and/or graded along the taper direction. The graded composition semiconductor material is substantially transparent to the light photons for photon energies substantially less than the bandgap. The above filter can also be aligned to a two-dimensional array of pixels to form a hyperspectral imager.

Abstract: In a multimode FPA, all of the FPA's conducting layers including all of the absorbing layers are patterned to form electrically isolated commons for at least two, and in some instances all of the photodetector sub-arrays, to support independent mode biasing of the photodetectors. Because the commons are electrically isolated, the bias voltages are not constrained by the CMOS design rules. The commons can accommodate large bias amplitude differences and different temporal bias profiles to address a wide range of multimode sensing applications.

Abstract: A cost-effective FPA includes a plurality of detectors per pixel, wherein radiation is directed by a microlens array into respective focal regions that are covered by the union of the detectors' collections regions within each pixel and any defective detectors are de-selected in the ROIC. The operability of each pixel is evaluated, and a map generated specifying detector de-selection for each pixel. This map is read into memory in the ROIC to de-select bad detectors. Bad detectors are preferably allowed to float to a photovoltage and re-emit some of their accumulated photo charge to neighboring detectors to improve collection efficiency. The radiation levels are preferably read out on a pixel-by-pixel basis. Accordingly, the signals from the selected detectors are combined within each pixel.