Patents by Inventor William Eli Thacker

William Eli Thacker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210242143
    Abstract: An electronic device includes: a base layer; a first layer located at least partially over the base layer; a second layer located at least partially over the first layer; a first metal layer located at least partially over the second layer, wherein one or more signal outputs of the electronic device are formed in the first metal layer; and a second metal layer located at least partially over the first metal layer, wherein one or more gate connection is formed in the second metal layer, wherein removing a portion of the second metal layer disrupts at least one gate connection and deactivates the device.
    Type: Application
    Filed: January 20, 2021
    Publication date: August 5, 2021
    Inventor: William Eli Thacker, III
  • Patent number: 10903175
    Abstract: An electronic device includes: a base layer; a first layer located at least partially over the base layer; a second layer located at least partially over the first layer; a first metal layer located at least partially over the second layer, wherein one or more signal outputs of the electronic device are formed in the first metal layer; and a second metal layer located at least partially over the first metal layer, wherein one or more gate connection is formed in the second metal layer, wherein removing a portion of the second metal layer disrupts at least one gate connection and deactivates the device.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: January 26, 2021
    Inventor: William Eli Thacker, III
  • Publication number: 20200058602
    Abstract: An electronic device includes: a base layer; a first layer located at least partially over the base layer; a second layer located at least partially over the first layer; a first metal layer located at least partially over the second layer, wherein one or more signal outputs of the electronic device are formed in the first metal layer; and a second metal layer located at least partially over the first metal layer, wherein one or more gate connection is formed in the second metal layer, wherein removing a portion of the second metal layer disrupts at least one gate connection and deactivates the device.
    Type: Application
    Filed: October 11, 2019
    Publication date: February 20, 2020
    Inventor: William Eli Thacker, III
  • Patent number: 10453807
    Abstract: An electronic device includes: a base layer; a first layer located at least partially over the base layer; a second layer located at least partially over the first layer; a first metal layer located at least partially over the second layer, wherein one or more signal outputs of the electronic device are formed in the first metal layer; and a second metal layer located at least partially over the first metal layer, wherein one or more gate connection is formed in the second metal layer, wherein removing a portion of the second metal layer disrupts at least one gate connection and deactivates the device.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: October 22, 2019
    Inventor: William Eli Thacker, III
  • Publication number: 20180261558
    Abstract: An electronic device includes: a base layer; a first layer located at least partially over the base layer; a second layer located at least partially over the first layer; a first metal layer located at least partially over the second layer, wherein one or more signal outputs of the electronic device are formed in the first metal layer; and a second metal layer located at least partially over the first metal layer, wherein one or more gate connection is formed in the second metal layer, wherein removing a portion of the second metal layer disrupts at least one gate connection and deactivates the device.
    Type: Application
    Filed: May 10, 2018
    Publication date: September 13, 2018
    Inventor: William Eli Thacker, III
  • Patent number: 10037950
    Abstract: It is desirable to design and manufacture electronic chips that are resistant to modern reverse engineering techniques. Disclosed is a method and device that allows for the design of chips that are difficult to reverse engineer using modern teardown techniques. The disclosed device uses devices having the same geometry but different voltage levels to create different logic devices. Alternatively, the disclosed uses devices having different geometries and the same operating characteristics. Also disclosed is a method of designing a chip using these devices.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: July 31, 2018
    Assignee: VERISITI, LLC
    Inventor: William Eli Thacker, III
  • Patent number: 9972398
    Abstract: A ROM circuit includes a first N channel transistor having an output and having device geometry and device characteristics adapted to bias the output at a predetermined level when a P channel circuit is connected to the first N channel transistor; a pass transistor connected between the output and a data bus, the pass transistor connected to a word line, the word line adapted to turn ON the pass transistor when the word line is asserted; and the P channel circuit connected to the data bus and adapted to provide leakage current to charge a gate in the first N channel transistor when pass transistor is turned ON.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: May 15, 2018
    Assignee: VERISITI, INC.
    Inventor: William Eli Thacker, III
  • Patent number: 9972585
    Abstract: An electronic device includes: a base layer; a first layer located at least partially over the base layer; a second layer located at least partially over the first layer; a first metal layer located at least partially over the second layer, wherein one or more signal outputs of the electronic device are formed in the first metal layer; and a second metal layer located at least partially over the first metal layer, wherein one or more gate connection is formed in the second metal layer, wherein removing a portion of the second metal layer disrupts at least one gate connection and deactivates the device.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: May 15, 2018
    Assignee: VERISITI, INC.
    Inventor: William Eli Thacker, III
  • Publication number: 20170117234
    Abstract: An electronic device includes: a base layer; a first layer located at least partially over the base layer; a second layer located at least partially over the first layer; a first metal layer located at least partially over the second layer, wherein one or more signal outputs of the electronic device are formed in the first metal layer; and a second metal layer located at least partially over the first metal layer, wherein one or more gate connection is formed in the second metal layer, wherein removing a portion of the second metal layer disrupts at least one gate connection and deactivates the device.
    Type: Application
    Filed: October 6, 2016
    Publication date: April 27, 2017
    Inventor: William Eli Thacker, III
  • Publication number: 20170087861
    Abstract: Electronic systems, such as printing systems, often use components that have integral memory. The integral memory can be used to store information about the component. In some printing systems this memory includes a portion that stores a value indicative of a print yield. Disclosed is a method and system for allowing the memory to have data indicative of an increased print yield.
    Type: Application
    Filed: December 9, 2016
    Publication date: March 30, 2017
    Inventors: William Eli Thacker, Scott M. Babish
  • Publication number: 20170092599
    Abstract: It is desirable to design and manufacture electronic chips that are resistant to modern reverse engineering techniques. Disclosed is a method and device that allows for the design of chips that are difficult to reverse engineer using modern teardown techniques. The disclosed device uses devices having the same geometry but different voltage levels to create different logic devices. Alternatively, the disclosed uses devices having different geometries and the same operating characteristics. Also disclosed is a method of designing a chip using these devices.
    Type: Application
    Filed: August 30, 2016
    Publication date: March 30, 2017
    Inventor: William Eli Thacker, III
  • Publication number: 20170062425
    Abstract: It is desirable to design and manufacture electronic chips that are resistant to modern reverse engineering techniques. Disclosed is a method and device that allows for the design of chips that are difficult to reverse engineer using modern teardown techniques. The disclosed device uses devices having the same geometry but different voltage levels to create different logic devices. Alternatively, the disclosed uses devices having different geometries and the same operating characteristics. Also disclosed is a method of designing a chip using these devices.
    Type: Application
    Filed: March 8, 2016
    Publication date: March 2, 2017
    Inventor: William Eli Thacker
  • Patent number: 9519449
    Abstract: Electronic systems, such as printing systems, often use components that have integral memory. The integral memory can be used to store information about the component. In some printing systems this memory includes a portion that stores a value indicative of a print yield. Disclosed is a method and system for allowing the memory to have data indicative of an increased print yield.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: December 13, 2016
    Assignee: Static Control Components, Inc.
    Inventors: William Eli Thacker, Scott M. Babish
  • Patent number: 9483003
    Abstract: A method of operating a cartridge chip installed in an imaging device includes: causing, by the cartridge chip, the imaging device to enter an error condition; monitoring the timing or sequence of communication signals received from the imaging device during at least a portion of the error condition; and operating, based on the timing or sequence of the communication signals received from the imaging device during at least a portion of the error condition, in a first mode of operation compatible with a first type of imaging device or in a second mode of operation compatible with a second type of imaging device.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: November 1, 2016
    Assignee: Static Control Components, Inc.
    Inventor: William Eli Thacker, III
  • Patent number: 9466576
    Abstract: An electronic device includes: a base layer; a first layer located at least partially over the base layer; a second layer located at least partially over the first layer; a first metal layer located at least partially over the second layer, wherein one or more signal outputs of the electronic device are formed in the first metal layer; and a second metal layer located at least partially over the first metal layer, wherein one or more gate connection is formed in the second metal layer, wherein removing a portion of the second metal layer disrupts at least one gate connection and deactivates the device.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: October 11, 2016
    Assignee: Verisiti, Inc.
    Inventor: William Eli Thacker, III
  • Patent number: 9437555
    Abstract: It is desirable to design and manufacture electronic chips that are resistant to modern reverse engineering techniques. Disclosed is a method and device that allows for the design of chips that are difficult to reverse engineer using modern teardown techniques. The disclosed device uses devices having the same geometry but different voltage levels to create different logic devices. Alternatively, the disclosed uses devices having different geometries and the same operating characteristics. Also disclosed is a method of designing a chip using these devices.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: September 6, 2016
    Assignee: Verisiti, Inc.
    Inventor: William Eli Thacker, III
  • Patent number: 9393799
    Abstract: Disclosed is a system and method for verifying a chip having a memory. Remanufacturers of imaging devices, such as inkjet printers or electrostatic printers, often have to use a replacement chip in order to reuse an imaging cartridge. It is desirable to have a system and method for determining if the replacement chip is suitable for use with a specific imaging cartridge. Also, it may be desirable to confirm that the chip was manufactured by a specific manufacturer. The disclosed system and method allow the remanufacturer a reliable and efficient way to verify chips.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: July 19, 2016
    Assignee: Static Control Components, Inc.
    Inventors: William Eli Thacker, III, Lynton R. Burchette, Scott Martin Babish
  • Publication number: 20160099219
    Abstract: It is desirable to design and manufacture electronic chips that are resistant to modern reverse engineering techniques. Disclosed is a method and device that allows for the design of chips that are difficult to reverse engineer using modern teardown techniques. The disclosed device uses devices having the same geometry but different voltage levels to create different logic devices. Alternatively, the disclosed uses devices having different geometries and the same operating characteristics. Also disclosed is a method of designing a chip using these devices.
    Type: Application
    Filed: October 2, 2014
    Publication date: April 7, 2016
    Applicant: Secure Silicon Layer, Inc.
    Inventor: William Eli Thacker, III
  • Patent number: 9304435
    Abstract: Electronic systems, such as printing systems, often use components that have integral memory. The integral memory can be used to store information about the component. In some printing systems this memory includes a portion that stores a value indicative of a print yield. Disclosed is a method and system for allowing the memory to have data indicative of an increased print yield.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: April 5, 2016
    Assignee: Static Control Components, Inc.
    Inventors: William Eli Thacker, Lynton R. Burchette, Scott M. Babish
  • Patent number: 9287879
    Abstract: It is desirable to design and manufacture electronic chips that are resistant to modern reverse engineering techniques. Disclosed is a method and device that allows for the design of chips that are difficult to reverse engineer using modern teardown techniques. The disclosed device uses devices having the same geometry but different voltage levels to create different logic devices. Alternatively, the disclosed uses devices having different geometries and the same operating characteristics. Also disclosed is a method of designing a chip using these devices.
    Type: Grant
    Filed: October 30, 2012
    Date of Patent: March 15, 2016
    Assignee: Verisiti, Inc.
    Inventor: William Eli Thacker