Abstract: The present invention is directed to determining the timing for a synchronous integrated circuit, the circuit including a multiplicity of clocked elements interconnected by signal paths. Predictions are formed for timing delays in said signal paths in the integrated circuit. A first such path is selected, wires are traced in the integrated circuit forming the path, hereinafter referred to as victim wires, and adjacent and crossing wires thereto, hereinafter referred to as aggressor wires, are determined. For each aggressor wire, the amount of electromagnetic coupling to the victim wires of the first path is determined. The aggressor wires are divided into a plurality of categories depending on the clocked timing of the aggressor wires in relation to the clocked timing of the victim wires.

Abstract: An integrated circuit device (10) comprises a semiconductor die (14) and an optical signal emitting diode (18) for communicating an optical signal, such as a clock or trigger signal, to individual circuits on the die (14). Each circuit includes a photosensitive active device implemented on the die for converting the received optical signal to an electronic signal for clocking or triggering a local circuit (e.g., a data storage register). Translucent material (20) encapsulates the emitter diode (18) and the die (14). The optically communicated signal has very low skew, which is independent of the topology of the die (14).

Abstract: An integrated circuit device including a semiconductor die and optical signal emitting diodes for communicating different color optical signals, such as multi-phase clock or trigger signals, to individual circuits on the die. Each circuit includes a filter to discriminate the desired frequency and a photosensitive active device implemented on the die for converting the received optical signal to an electronic signal for clocking or triggering a local circuit (e.g., a data storage register). Translucent material encapsulates the emitter diode and the die. The optically communicated signal has very low skew, which is independent of the topology of the die.

Abstract: An integrated circuit having a die with one or more electrical input cells and one or more optical input cells. The cells are arranged together in an array, and the cells may have generally the same size and equivalent geographies, to permit standard electrical-only tools and practices to be used for designing the die.

Abstract: An analog to digital converter has an analog signal input, reference voltage divider and a plurality of comparators. Each comparator has a first input connected to said analog signal input and a reference input connected to receive a respective predetermined reference voltage from the reference voltage divider. In addition, test mode circuitry is provided for feeding a sequence of test voltages from the voltage divider to the first input of the comparators in a test mode. A decoder is connected to an output of each comparator for generating a binary output signal representative of an input analog signal.