Abstract: An integrated demodulator tuning circuit (10, 60) receives differential currents at input terminals (12, 46) and provides an AFC signal at an output terminal (48). The AFC current characteristic has a dead band (72) in the output current generated when the integrated demodulator tuning circuit (10, 60) operates under the condition where the difference between the currents supplied at the input terminals (12 and 46) is at or below a set threshold value. The set threshold value is determined by the relative sizes of the transistors (14, 16 and 20, 36, 38 and 40) that form the current mirrors connected to the input terminals (12, 46).

Abstract: A demodulator circuit (10) having harmonic cancelling receives an input signal (IF) and generates an oscillator signal (OSC) in an oscillator circuit (14). The oscillator signal (OSC) is locked to the same frequency and phase as the input signal (IF). A phase shift circuit (18) generates a shifted signal (OSC SHIFTED) that is in quadrature with the oscillator signal (OSC). A multiplier (22) receives the oscillator signal (OSC) and the shifted signal (OSC SHIFTED) and generates an output signal (2IF) having twice the frequency of the oscillator signal (OSC). A multiplier circuit (24) also receives the input signal (IF) and along with the oscillator signal (OSC) generates an output signal (PD). The signals generated by the multiplier (22) and the multiplier circuit (24) are summed in a summing circuit (30) that supplies an output signal (OUT).

Abstract: An integrated demodulator tuning circuit (10, 60) receives differential currents at input terminals (12, 46) and provides an AFC signal at an output terminal (48). The AFC current characteristic has a dead band (72) in the output current generated when the integrated demodulator tuning circuit (10, 60) operates under the condition where the difference between the currents supplied at the input terminals (12 and 46) is at or below a set threshold value. The set threshold value is determined by the relative sizes of the transistors (14, 16 and 20, 36, 38 and 40) that form the current mirrors connected to the input terminals (12, 46).

Abstract: A demodulator circuit (10) having harmonic cancelling receives an input signal (IF) and generates an oscillator signal (OSC) in an oscillator circuit (14). The oscillator signal (OSC) is locked to the same frequency and phase as the input signal (IF). A phase shift circuit (18) generates a shifted signal (OSC SHIFTED) that is in quadrature with the oscillator signal (OSC). A multiplier (22) receives the oscillator signal (OSC) and the shifted signal (OSC SHIFTED) and generates an output signal (21F) having twice the frequency of the oscillator signal (OSC). A multiplier circuit (24) also receives the input signal (IF) and along with the oscillator signal (OSC) generates an output signal (PD). The signals generated by the multiplier (22) and the multiplier circuit (24) are summed in a summing circuit (30) that supplies an output signal (OUT).

Abstract: A demodulator circuit (10) includes an oscillator (12) and an injection circuit (14). An Automatic Frequency Control (AFC) signal adjusts the tail current of a current source (28) provided in the oscillator (12) and the tail current of a current source (44) provided in the injection circuit (14). A phase detector (16) compares the phase of the signal generated by the oscillator (12) with the phase of the injected input signal. The phase detector (16) generates an output signal V0 having a value of zero when the input signal is in quadrature with the signal generated by the oscillator (12), but generates a non-zero signal that is used to adjust the AFC signal when the input signal and the signal generated by the oscillator (12) are not in quadrature.

Abstract: A circuit for doubling the frequency of an input signal. The circuit includes a full-wave rectifier that rectifies the input signal to generate an output signal with double the frequency of the input signal. The output signal is compared to a predetermined voltage. Based on this comparison, a control signal is fed back to the full-wave rectifier and the output of the rectifier is adjusted to a predetermined level. In this manner the frequency of the input signal is doubled, and the output power is maintained constant, independent of the input power level.

Abstract: A linear differential gain stage (31) has a first input (32), a second input (33), a first output (34), and a second output (35). A differential input voltage is coupled to an input differential transistor pair (39,40). Voltage compensation circuits (53,54) cancel non-linearities due to the input differential transistor pair (39,40). Parasitic capacitance of the input differential transistor pair (39,40) couple current to the first and second inputs (32,33) due to voltage transitions at the first and second outputs (34,35). The current to the first and second inputs (32,33) is canceled by impedance compensation circuits (55,56) that provide an equal magnitude but opposite sign current. The result is an almost infinite input impedance to the linear differential gain stage (31).

Abstract: A current mirror circuit (31) that includes an active loop which operates transistors of different conductivity type at equal base-emitter junction voltages to minimize error. A first resistor (38) couples to a base of a first transistor (32) of a first conductivity type in a voltage follower configuration. A reference current is coupled to the first resistor (38). The voltage across the first resistor (38) and base-emitter junction of the first transistor (32) is mirrored across the base-emitter junction of a second transistor (34) of a second conductivity type and a second resistor (39). A third transistor (35) of the second conductivity type in a diode configuration is coupled to receive current from the second transistor (34). The voltage across the third transistor (35) biases a fourth transistor (33) of a first conductivity type. The current from the fourth transistor (33) is provided to the first transistor such that the first and second transistors (32,34) operate at equal base-emitter voltages.

Abstract: A demodulator circuit (100) and method for producing a demodulated signal V.sub.OUT from an input signal V.sub.IN. A frequency detection circuit (101) produces a quadrature signal V.sub.QUAD which is compared to the input signal V.sub.IN to produce a detected output signal. The phase and frequency of the quadrature signal V.sub.QUAD are responsive to a control signal I.sub.CONTROL. The demodulator circuit (100) has an output terminal (114) which provides the demodulated signal V.sub.OUT. Nonlinearity in the demodulated output signal V.sub.OUT in relation to a modulating signal is reduced by a linearizing feedback circuit (102). Automatic tuning is provided by a tuning feedback circuit (103). The output signals produced at the respective output terminals (114) and (113) of the linearizing feedback circuit (102) and tuning feedback circuit (103) are summed to produce the control current I.sub.CONTROL.

Abstract: A buffer amplifier suitable for being driven by a differential amplifier having a differential-to-single ended converter is disclosed. The buffer amplifier includes a multi-collector input transistor of a first conductivity type and an emitter-follower output transistor of a second conductivity type. The base of the output transistor is connected to a first collector of the input transistor. A bias circuit for the output transistor is connected to the first collector of the input transistor and to the base of the output transistor. A negative feedback network is connected between the emitter of the output transistor and the base and second collector of the input transistor to stabilize the quiescent output voltage. Current sources are utilized for maximizing the amplitude of the dynamic output voltage and for facilitating temperature independence.