Abstract: A circuit 17 for interfacing with a sensor 18 having a sensor input current and a modulated sensor current signal corresponding to a sensed condition. A control module 20 is coupled to the sensor 18 and receives the sensor current signal. The control module 20 converts the sensor current signal to a modulated signal having a pulse width with a duration corresponding to the sensed condition. The control module 20 counts a time corresponding to the pulse width. The time corresponds to the sensed condition.

Abstract: Burst memory transfer from a memory to a microprocessor (CPU) is accomplished using analysis including determining first and second conditions. If an output enable is consecutively activated for more than one consecutive system clock cycle, following the address phase, the memory will initiate a burst transfer sequence. The addresses of subsequent data bytes or words following the first byte or word are determined by the memory advancing or incrementing its internal address counter until the burst transfer has been suspended or terminated. If the output enable pin is deactivated prior to the next address phase requested by the CPU, burst transfer will be suspended until the output enable pin is activated again. If the CPU requests the next address phase (chip enable activated) from the memory while the output enable is activated, the burst in progress will be terminated.