Abstract: A data storage system having a plurality of disk drive sections, each one of the disk drive sections having a plurality of disk drives. Each one of a plurality of secondary SAS expanders is coupled to a corresponding one of the disk drive sections. Each one of the secondary SAS expanders has: (1) a plurality of first ports each one being connected to a corresponding one of the disk drives in the corresponding one of the plurality of disk drive sections coupled thereto; and (2) a second port. A main SAS expander has: (1) a first port; and (2) N second ports, each one of the N second ports of the main expander being connected to the second port of a corresponding one of the plurality of N secondary expanders. A storage processor is coupled to the second port of the main SAS expander.

Abstract: A data transfer system includes a PCI Express transaction layer having an input for serially receiving posted and non-posted request packets and completion packets; an application layer coupled to the PCI Express transaction layer for receiving posted and non-posted request packets and completion packets from the PCI Express transaction layer; a first transmission interface coupling the application layer to the PCI Express transaction layer; and a second transmission interface coupling the application layer to the PCI Express transaction layer. The PCI Express transaction layer transmits posted and non-posted request packets to the application layer over the first transmission interface and transmits completion packets to the application layer over the second transmission interface.

Abstract: A method is provided for transmitting user data from a selected one of a plurality of data pipes. The method includes having a ring manager select one of the data pipes from a pool of the data pipes for transmission of the user data. The data is transmitted from the selected one of the data pipes at least one packet switching network. The data pipe detects whether there was an error in the transmission. If there an error detected, the data pipe generates an error interrupt for the ring manager. The ring manager detects the error interrupt and generates an error interrupt for a CPU. The ring manager removes the selected one of the data pipes from the pool of data pipes for a predetermined period of time while the ring manager continues to work on other tasks until the time has expired. During pipe retirement, the physical pipe removed from the pool of pipes is disabled and the router will then direct orphan packets to the error ring.

Abstract: Described are techniques for determining a set of routing information for a plurality of components performing routing in a network. Destinations that are directly connected to each of the plurality of components are determined. Each of the plurality of components is associated with one of a plurality of routing tables. Each of the plurality of routing tables stores routing information in accordance with destinations in the network. Cost information is stored in the plurality of routing tables for each destination directly connected to one of the plurality of components. For each of the plurality of components, a set of neighboring components is determined. For each neighboring component, routing information for a destination is adopted from the routing table of said each neighboring component in accordance with an adoption rule. Processing is repeatedly performed until the routing tables have not been modified.

Abstract: A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller bypasses a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.

Abstract: A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller passes a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.

Abstract: A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller bypasses a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.

Abstract: A data storage system having a packet switching network, a cache memory, and a plurality of directors, one portion of such directors being adapted for coupling to a host computer/server and another portion of the directors being adapted for coupling to a bank of disk drives. The plurality of directors and cache memory are interconnected through the packet switching network. Each one of the directors is adapted to transmit different types of information packets to another one of the directors through the network. Each one of the directors is adapted to transmit and receive different types of information packets to another one of the directors or cache memories through the packet switching network. Each one of the cache memories is adapted to receive and transmit different types of information packets to one of the directors through the packet switching network. One type of information packet requires a different degree of latency than another type of information packet.

Abstract: A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller bypasses a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.

Abstract: An end point controller includes two of ingress/egress port pairs. A first one of the ingress/egress ports is adapted to send and receive one of a pair of types of information packets and a second one of the ingress/egress ports is adapted to send and receive the other one of the pair of types of information packets. A controller is coupled to the two port pairs for coupling one of ingress/egress ports to an input/output port selectively in accordance with the type of the information packet on the ingress/egress ports and the availability of the end point controller to a network. One of the egress ports is directly coupled to the output port to the network if the information packet is at such port and the end point controller has been granted access to the network while other information at the pair of egress ports is buffered prior to being coupled to the output.

Abstract: A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller bypasses a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.

Abstract: A method is provided for performing arbitration in an information packet controller. The method includes transmitting different types of information packets from an initiator to a receiver. One type of information packet has a quality of service requiring a faster transmission time from the initiator to the receiver than another type of information packet having a quality of service having a slower transmission time from the initiator to the receiver. The transmitting of the information packets from the initiator to the receiver is in accordance with priority assigned to the information packet, the quality of service assigned to the information packet, and the age of such information packets having been stored in a queue of the initiator, such quality of service being a function of the speed at which the packets are required to pass from the initiator to a receiver.

Abstract: A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller bypasses a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.

Abstract: A queuing system wherein at least one input/output (I/O) interface having an outbound queue. A plurality of processing units is coupled to the at least one I/O interface. Each one of the processing units is coupled to a corresponding processing unit memory. Each one of the processing unit memories has an inbound queue for such coupled processing unit. The at least one I/O interface outbound queue stores outbound information being returned to the I/O interface after being processed by one of the processing units. The I/O interface creates queue indices for storage in the inbound queues of the processor unit memories. The I/O interface includes a translation table, such table storing at a location a producer index for the plurality of processing units and a consumer index for such plurality of processing units.

Abstract: A system interface having a plurality of directors, one portion of such directors being adapted for coupling to a host computer/server and another portion of the directors being adapted for coupling to a bank of disk drives. The plurality of directors are interconnected through a network. A common resource section is provided having a resource shared among the plurality of directors. The common shared resource section includes a shared computer code used by the plurality of directors. The code includes computer code for booting up each one of the plurality directors. The common shared code storage section is interconnected to the directors through the network. A second, redundant common shared resource section is provided. The network is a packet switching network.

Abstract: A data storage system wherein a data controlling director examines the contents of the tag to determine whether requested read data exists in a local cache memory having this data controlling director or in some other local memory cache, or in a disk drive coupled to this data controlling director; and if the requested read data does exist in the local cache memory having this data controlling director, or in the disk drive coupled to director; the data controlling director sends a copy to the local cache memory of the read request receiving director; updates its tag to show a shared copy will reside in the requesting director's local cache memory; and also sends a message to the read requesting director indicating the data is available for storage in the local cache memory on said one of the plurality of first director/memory boards having the read request receiving director.

Abstract: A system interface having: a packet switching network; a cache memory; and a plurality of directors. One portion of such directors is adapted for coupling to a host computer/server and another portion of the directors is adapted for coupling to a bank of disk drives, the plurality of directors and cache memory being interconnected through the packet switching network. Each one of the directors is coupled to a crossbar switch. The cross bar switch is directly connected to at least two other ones of the cross bar switches networks and indirectly connected to of other ones of the crossbar switches through the at least two directly connected crossbar switches.

Abstract: A system interface having: a plurality of front end directors adapted for coupling to a host computer/server; a plurality of back end directors adapted for coupling to a bank of disk drives; a data transfer section having cache memory; a cache memory manager; and, a message network. The cache memory is coupled to the plurality of front end and back end directors. The messaging network operates independently of the data transfer section and is coupled to the plurality of front end and back end. The front end and back end directors control data transfer between the host computer/server and the bank of disk drives in response to messages passing between the front end directors and the back end directors through the messaging network to facilitate data transfer between host computer/server and the bank of disk drives. The data passes through the cache memory in the data transfer section as such data passes between the host computer and the bank of disk drives.

Abstract: A high availability computer system and methodology including a backplane, having at least one backplane communication bus and a diagnostic bus, a plurality of motherboards, each interfacing to the diagnostic bus. Each motherboard also includes a memory system including main memory distributed among the plurality of motherboards and a memory controller module for accessing said main memory interfacing to said motherboard communication bus. Each motherboard also includes at least one daughterboard, detachably connected to thereto. The motherboard further includes a backplane diagnostic bus interface mechanism interfacing each of the motherboards to the backplane diagnostic bus; a microcontroller for processing information and providing outputs and a test bus controller mechanism including registers therein.

Abstract: A very fast, memory efficient, highly expandable, highly efficient CCNUMA processing system based on a hardware architecture that minimizes system bus contention, maximizes processing forward progress by maintaining strong ordering and avoiding retries, and implements a full-map directory structure cache coherency protocol. A Cache Coherent Non-Uniform Memory Access (CCNUMA) architecture is implemented in a system comprising a plurality of integrated modules each consisting of a motherboard and two daughterboards. The daughterboards, which plug into the motherboard, each contain two Job Processors (JPs), cache memory, and input/output (I/O) capabilities. Located directly on the motherboard are additional integrated I/O capabilities in the form of two Small Computer System Interfaces (SCSI) and one Local Area Network (LAN) interface. The motherboard includes main memory, a memory controller (MC) and directory DRAMs for cache coherency.