Abstract: Process for etching features in wafers incorporating OSG dielectrics. The process results at once in minimal RIE lag, minimal bowing of the features formed by the etch process, good etch profiles, good resist selectivity, and good etch uniformity across the wafer. In order to provide these desirable results, a novel etch gas mixture, including CH2F2 and CF4 is employed. According to one embodiment of the present invention, this novel gas mixture is employed as part of a three-step etch process wherein the several etch steps have varying degrees of etch selectivity between wafer components. The methodology of the present invention is capable of implementation on a wide variety of existing semiconductor etch equipment.

Abstract: A dry etching process for use in the manufacture of silicon integrated circuit devices uses a mixture of about eight parts neon to one part CHF.sub.3 (Freon 23) to form the etching plasma. The process etches doped oxides of silicon, such as BPSG and BPTEOS, in preference to undoped oxides of silicon, silicon nitride, silicides and silicon.

Abstract: A dry etching process for use in the manufacture of silicon integrated circuit devices uses a mixture of about eight parts neon to one part CHF.sub.3 (Freon 23) to form the etching plasma. The process etches doped oxides of silicon, such as BPSG and BPTEOS, in preference to undoped oxides of silicon, silicon nitride, silicides and silicon.