Patents by Inventor William F. Burghout
William F. Burghout has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9847219Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer having a layer of material by placing the semiconductor wafer onto a carrier tape with the layer of material adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the layer of material within the singulation lines, and separating portions of the layer of material using a fluid.Type: GrantFiled: September 16, 2016Date of Patent: December 19, 2017Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: William F. Burghout, Dennis Lee Conner, Michael J. Seddon, Jay A. Yoder, Gordon M. Grivna
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Publication number: 20170004965Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer having a layer of material by placing the semiconductor wafer onto a carrier tape with the layer of material adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the layer of material within the singulation lines, and separating portions of the layer of material using a fluid.Type: ApplicationFiled: September 16, 2016Publication date: January 5, 2017Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: William F. BURGHOUT, Dennis Lee CONNER, Michael J. SEDDON, Jay A. YODER, Gordon M. GRIVNA
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Patent number: 9484210Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer having a backmetal layer by placing the semiconductor wafer onto a carrier tape with the backmetal layer adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the backmetal layer within the singulation lines, and separating portions of the backmetal layer using a fluid.Type: GrantFiled: April 20, 2015Date of Patent: November 1, 2016Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: William F. Burghout, Dennis Lee Conner, Michael J. Seddon, Jay A. Yoder, Gordon M. Grivna
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Publication number: 20150228494Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer having a backmetal layer by placing the semiconductor wafer onto a carrier tape with the backmetal layer adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the backmetal layer within the singulation lines, and separating portions of the backmetal layer using a fluid.Type: ApplicationFiled: April 20, 2015Publication date: August 13, 2015Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: William F. Burghout, Dennis Lee Conner, Michael J. Seddon, Jay A. Yoder, Gordon M. Grivna
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Patent number: 9034733Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer having a backmetal layer by placing the semiconductor wafer onto a carrier tape with the backmetal layer adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the backmetal layer within the singulation lines, and separating portions of the backmetal layer within the singulation lines using a pressurized fluid applied to the carrier tape.Type: GrantFiled: January 21, 2014Date of Patent: May 19, 2015Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: William F. Burghout, Dennis Lee Conner, Michael J. Seddon, Jay A. Yoder, Gordon M. Grivna
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Publication number: 20140134828Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer having a backmetal layer by placing the semiconductor wafer onto a carrier tape with the backmetal layer adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the backmetal layer within the singulation lines, and separating portions of the backmetal layer within the singulation lines using a pressurized fluid applied to the carrier tape.Type: ApplicationFiled: January 21, 2014Publication date: May 15, 2014Applicant: Semiconductor Components Industries, LLCInventors: William F. Burghout, Dennis Lee Conner, Michael J. Seddon, Jay A. Yoder, Gordon M. Grivna
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Patent number: 8664089Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer having a backmetal layer by placing the semiconductor wafer onto a carrier tape with the backmetal layer adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the backmetal layer within the singulation lines, and fluid machining the semiconductor wafer to remove the backmetal layer from the singulation lines.Type: GrantFiled: August 20, 2012Date of Patent: March 4, 2014Assignee: Semiconductor Components Industries, LLCInventors: William F. Burghout, Dennis Lee Conner, Michael J. Seddon, Jay A. Yoder
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Publication number: 20140051232Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer having a backmetal layer by placing the semiconductor wafer onto a carrier tape with the backmetal layer adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the backmetal layer within the singulation lines, and fluid machining the semiconductor wafer to remove the backmetal layer from the singulation lines.Type: ApplicationFiled: August 20, 2012Publication date: February 20, 2014Inventors: William F. Burghout, Dennis Lee Conner, Michael J. Seddon, Jay A. Yoder
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Patent number: 8319323Abstract: In one embodiment, a leadless package includes down-set conductive leads having base portions. The base portions include stand-offs that attach to electrodes on an electronic chip using, for example, a solder die attach material. An optional encapsulating layer covers portions of the down-set conductive leads and portions of the electronic chip while leaving pad portions of the down-set conductive leads and a surface of the electronic chip exposed. The pad portions and the surface of the electronic chip are oriented to attach to a next level of assembly.Type: GrantFiled: December 20, 2004Date of Patent: November 27, 2012Assignee: Semiconductor Components Industries, LLCInventors: James P. Letterman, Jr., Joseph K. Fauty, Jay A. Yoder, William F. Burghout
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Patent number: 7820528Abstract: In one embodiment, a method for forming a leaded molded array package includes placing a lead frame assembly into a molding apparatus having lead cavities. The method further includes forming seals between conductive leads within the lead frame assembly and the lead cavities, and encapsulating the lead frame assembly to form a molded array assembly. The molded array assembly is then separated into individual leaded molded packages.Type: GrantFiled: August 4, 2009Date of Patent: October 26, 2010Assignee: Semiconductor Components Industries, LLCInventors: William F. Burghout, Francis J. Carney, Joseph K. Fauty, James P. Letterman, Jay A. Yoder
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Publication number: 20100000772Abstract: In one embodiment, a leadless package includes down-set conductive leads having base portions. The base portions include stand-offs that attach to electrodes on an electronic chip using, for example, a solder die attach material. An optional encapsulating layer covers portions of the down-set conductive leads and portions of the electronic chip while leaving pad portions of the down-set conductive leads and a surface of the electronic chip exposed. The pad portions and the surface of the electronic chip are oriented to attach to a next level of assembly.Type: ApplicationFiled: December 20, 2004Publication date: January 7, 2010Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, L.L.C.Inventors: James P. Letterman, JR., Joseph K. Fauty, Jay A. Yoder, William F. Burghout
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Publication number: 20090298232Abstract: In one embodiment, a method for forming a leaded molded array package includes placing a lead frame assembly into a molding apparatus having lead cavities. The method further includes forming seals between conductive leads within the lead frame assembly and the lead cavities, and encapsulating the lead frame assembly to form a molded array assembly. The molded array assembly is then separated into individual leaded molded packages.Type: ApplicationFiled: August 4, 2009Publication date: December 3, 2009Inventors: William F. Burghout, Francis J. Carney, Joseph K. Fauty, James P. Letterman, Jay A. Yoder
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Patent number: 7588999Abstract: In one embodiment, a method for forming a leaded molded array package includes placing a lead frame assembly into a molding apparatus having lead cavities. The method further includes forming seals between conductive leads within the lead frame assembly and the lead cavities, and encapsulating the lead frame assembly to form a molded array assembly. The molded array assembly is then separated into individual leaded molded packages.Type: GrantFiled: October 28, 2005Date of Patent: September 15, 2009Assignee: Semiconductor Components Industries, LLCInventors: William F. Burghout, Francis J. Carney, Joseph K. Fauty, James P. Letterman, Jay A. Yoder
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Patent number: 6081031Abstract: An electronic component includes a substrate (301, 801), a leadframe (101, 601, 710) coupled to a first surface of the substrate (301, 801) and extending beyond the first surface and towards a second surface of the substrate (301, 801), and an electrically conductive layer coupled to the second surface and coplanar with a contact portion of the leadframe (101, 601, 710) where the leadframe (101, 601, 710) and the electrically conductive layer form a package around the substrate (301, 801).Type: GrantFiled: June 29, 1998Date of Patent: June 27, 2000Assignee: Semiconductor Components Industries, LLCInventors: James P. Letterman, Jr., Albert J. Laninga, James H. Knapp, Joseph K. Fauty, William F. Burghout