Abstract: A charge coupled device includes a substrate; a plurality of image pixels arranged in a two dimensional array in the substrate for capturing an electronic representation of an image and for transferring charge in a first direction; a transfer mechanism for transferring charge in a second direction from the plurality of the image pixels for further processing; an amplifier structure disposed in the substrate that receives the charge from the transfer mechanism and converts the charge into a voltage signal; a first opaque layer spanning over the amplifier for blocking near-infrared light inherently generated by an electrical field within the amplifier structure when a voltage is applied; and a second opaque layer deposited into the substrate for also blocking near-infrared light inherently generated by an electrical field within the amplifier structure when a voltage is applied.

Abstract: A timing generator for an electronic image sensor includes one or more memory based tables for controlling timing events that occur within one or more different types of image sensor lines, and one or more memory based tables for controlling timing events that occur within one or more different types of image sensor frames.

Abstract: A timing generator for an electronic image sensor includes one or more memory based tables for controlling timing events that occur within one or more different types of image sensor lines, and one or more memory based tables for controlling timing events that occur within one or more different types of image sensor frames.

Abstract: A structure for a fast-dump gate for charge coupled devices that does not require a separate contact to a drain region instead using the existing drain of a lateral overflow drain (LOD) typically used for antiblooming purposes. LOD structures are typically used on full-frame CCD image sensors. By using the LOD as the drain for a fast-dump gate, a separate opening in the gate electrode for the drain contact is avoided, thereby making the structure more compact. Gate control is provided by etching a hole in the CCD gate electrode over the overflow channel region of the LOD structure, and overlaying this with one of the subsequent gate electrode layers. This subsequent gate electrode is then used to control the fast-dump operation. Timing is shown for a two-phase CCD being operated with accumulation-mode clocking. Other types of CCDs and clocking schemes may be used.

Abstract: A charge-coupled device having an improved charge-transfer efficiency over a broad temperature range.

Abstract: Apparatus and a method for the packaging of semiconductor chips to simplify assembly while improving thermal dissipation from the chip and reducing stress in the chip due to differential thermal expansion between the chip and its package as they are cycled over a temperature range are disclosed. An adhesive tape covers an active area of the chip and leaving bonding pads on the chip exposed through a recess in the adhesive tape. A body with a similar recess supports the other side of the tape. Wire bonds are made in the recess to connect bonding pads on the body to the chip. A lid covers the recess to protect the wire bonds.