Abstract: An active over-voltage clamp system includes at least one over-voltage detector that is responsive to an input voltage and provides a first current. The system also includes a replica over-voltage circuit that provides a second current, and circuitry subtracting the second current from the first current to produce a difference current. The system further includes a differential clamp activated in response to the difference current. The differential clamp prevents the input voltage from increasing beyond a target voltage.

Abstract: An active over-voltage clamp system includes at least one over-voltage detector that is responsive to an input voltage and provides a first current. The system also includes a replica over-voltage circuit that provides a second current, and circuitry subtracting the second current from the first current to produce a difference current. The system further includes a differential clamp activated in response to the difference current. The differential clamp prevents the input voltage from increasing beyond a target voltage.

Abstract: Equalization techniques in clock recovery receivers may include use of a passive equalizer prior to amplification, combined frequency paths in and active and/or passive equalizer, capacitive degeneration and/or negative feedback with low-pass filtering in an active equalizer, a decision feedback equalizer with multiple decision paths, and programmable tail currents to change switching points. A compensation circuit for a pre/post equalizer may include an oscillator fabricated from replica components to compensate for process variations and a look-up table to provide process variation correction in response to programmed equalizer settings.

Abstract: A system and method of calibration develops a function from which is generated a monotonic time response; a gating period is defined from the monotonic time response and any error in the frequency of a reference signal is determined during the gating period; from that error an error signal is generated for adjusting the time constant of a circuit to be calibrated.

Abstract: A digital phase acquisition clock recovery circuit includes a digital phase-locked loop that employs a truth table decoder to set the actual delay through a plurality of individual delay elements to generate a plurality of clock phase signals approximately equally spaced in time over one reference clock cycle, and a data sampler circuit that generates a plurality of received data samples from an incoming data sample taken at the rising edge of the respective clock phase signals and synchronizes the data samples to reference clock on a bit period-by-bit period basis. A digital phase acquisition circuit includes an edge detector which evaluates the data samples over each bit period to detect the location of a transition between respective adjacent samples, wherein logic is employed to continually determine the "relative quality" of each data sample, based upon its sampling time being furthest from a detected edge transition.

Abstract: A combined signalling and PCM cross-connect and packet assembly/disassembly engine includes a cross-connect memory, wherein the memory advantageously includes both a subscriber PCM channel memory that cross-connects bus side PCM channels to optical fiber timeslots, and a separate signalling memory that cross-connects associated signalling data channels to optical fiber timeslots. In particular, the PCM and signalling data memories are substantially the same size and each signalling data channel is mapped to an address in the signalling memory that corresponds to the PCM memory address of the associated PCM channel. Cross-connect information used for the PCM channels is also used to cross-connect the associated signalling channels. Cross-connect and packet engine functions are combined, thereby eliminating the need for a separate buffer to accommodate differences in transmission rates between them.

Abstract: A dc-coupled receiver for a shared optical system includes an input feedback amplifier circuit which establishes a dc reference baseline voltage level for incoming packets of data. A pair of sample-and-hold circuits are connected in parallel to receive and sample signals from the feedback amplifier circuit when no data is being transmitted and at the initial edge of incoming packets of data. A voltage divider circuit receiving signals from the sample-and-hold circuits establishes a dc slicing level for each incoming packet of data. An output feedback circuit can be added to compensate for offset error without affecting the performance of the sample-and-hold circuitry.

Abstract: An office interface unit (OIU) transfers data and signaling between a telephone local exchange and distribution lines. Information from the telephone local exchange is contained in repetitive frames containing signaling time slots which each contain two distinct nibbles of information. The OIU translates each local exchange signaling channel into first and second internal signaling channels, each internal signaling channel containing information representative of one signaling nibble therein. This simplifies DSO time slot interchange in the OIU. In addition, each internal signaling channel is provided with at least one additional significant signaling bit thereby providing additional signaling states so that the OIU equipment can account for multiple types of telephone local exchange equipment easily.

Abstract: An inrush current limiting circuit in accordance with the principles of the present invention limits initial current flow to a highly initially reactive power load. The current limiting circuit comprises a plug in connection to a power source and two conductor paths leading from the plug in connection. A power FET has a source element to drain element path in series with one of the conductor paths and has a gate connection. A bipolar transistor is connected to shunt the gate element of the power FET to the potential at its source element when the bipolar transistor is conducting, thereby to limit the current passing through the power FET. A sense resistor is in series with one of the conductor paths for controlling a base element of the bipolar transistor to cause it to conduct when current through the sense resistor exceeds a predetermined amount.

Abstract: Movement of a tool relative to a workpiece along each one of a plurality of axes is controlled by digitally providing a train of digital pulses to an electromechanical actuator and by digitally modulating the pulse widths (without an intervening conversion to analog form) so that electrical energy is carried in the pulse train at rates which will cause the actuator to tend to produce an intended sequence of speeds and positions.