Abstract: A number of architectures of switch compensation networks are described for the provision of a compensation current which ensures the maintaining of a desired switching ratio in an acoustic printhead. The described architectures include those which provide column compensation, row compensation, and row and column compensation to a transducer switching matrix. Control of the switching ratio by the compensation networks, is used in consideration of the dissipation of heat energy through expulsion of a heated drop, to provide a precisely controlled balance.

Abstract: A multi-level hierarchical bus architecture implemented with a multi-chip package and a modular shared-bus provides high bandwidth. All IC components are mounted on standardized multi-chip packages. Each multi-chip package includes bus interface chips for providing communication from the integrated circuits to a board bus. One multi-chip package contains additional bus interface circuitry for providing communication from the board bus to a backplane bus.

Abstract: A multi-level hierarchical bus architecture implemented with a multi-chip package and a modular shared-bus provides high bandwidth. All IC components are mounted on standardized multi-chip packages. Each multi-chip package includes bus interface chips for providing communication from the integrated circuits to a board bus. One multi-chip package contains additional bus interface circuitry for providing communication from the board bus to a backplane bus.

Abstract: A multi-level hierarchical bus architecture implemented with a multi-chip package and a modular shared-bus provides high bandwidth. All IC components are mounted on standardized multi-chip packages. Each multi-chip package includes bus interface chips for providing communication from the integrated circuits to a board bus. One multi-chip package contains additional bus interface circuitry for providing communication from the board bus to a backplane bus.

Abstract: An integrated sample and hold circuit includes a capacitor that is charged through a channel, such as a first input transistor's channel. Feedback circuitry connected to the first transistor's channel leads maintains approximately zero voltage difference between the channel leads to prevent leakage current when the first transitor is turned off. Isolation circuitry, such as a second input transistor, isolates the first transistor from the input voltage while a voltage level is being stored, and the gates of both input transistors can be connected to receive the same store signal. The feedback circuitry can include a follower transistor with its gate connected to the first transistor's output lead and a first channel lead connected to the first transistor's input lead and to load circuitry that maintains current flow through the follower transistor. To ensure that it does not pass current to or from the capacitive element, the follower transistor can be an MOS device or other insulated gate transistor.

Abstract: This invention provides very wide channel, open drain, N-channel CMOS drivers and cascode CMOS receivers for interfacing VLSI CMOS circuits to transmission lines which are terminated by their characteristic resistive impedances to voltage levels on the order of about 1.2 v-2.0 v. These GTL (a coined descriptor) drivers and receivers typically operate with a voltage swing on the order of about 0.8 v-1.4 v on such transmission lines for carrying out binary communications between CMOS circuits configured to operate with standard 5 v rail-to-rail voltage swings for their internal signals.

Abstract: A reproduction scanning system having intermediate storage between input and output scanning stations wherein an input document is scanned in first and second directions, the first direction being orthogonal to said second direction, and the electrical signals representative of information on said scanned document being stored on an intermediate storage member for storage, signal processing or data manipulation. The information stored in the storage member may be read out and reproduced on a reproducing medium. Other system features include input scan reversal for alternate bound pages during bound volume scanning, synchronization of the system by a clock associated with the storage member, input/output interleaving with a print interrupt feature, image centering and edge fadeout for image reduction, and independent magnification demagnification by separately variable raster spacing.

Abstract: A reproduction scanning system having intermediate storage between input and output scanning stations wherein an input document is scanned in first and second directions, the first direction being orthogonal to said second direction, and the electrical signals representative of information on said scanned document being stored on an intermediate storage member for storage, signal processing or data manipulation. The information stored in the storage member may be read out and reproduced on a reproducing medium. Other system features include input scan reversal for alternate bound pages during bound volume scanning, synchronization of the system by a clock associated with the storage member, input/output interleaving with a print interrupt feature, image centering and edge fadeout for image reduction, and independent magnification demagnification by separately variable raster spacing.

Abstract: A reproduction scanning system having intermediate storage between input and output scanning stations wherein an input document is scanned in first and second directions, the first direction being orthogonal to said second direction, and the electrical signals representative of information on said scanned document being stored on an intermediate storage member for storage, signal processing or data manipulation. The information stored in the storage member may be read out and reproduced on a reproducing medium. Other system features include input scan reversal for alternate bound pages during bound volume scanning, synchronization of the system by a clock associated with the storage member, input/output interleaving with a print interrupt feature, image centering and edge fadeout for image reduction, and independent magnification demagnification by separately variable raster spacing.

Abstract: A motor speed control system for reducing instantaneous speed variations as a result of hunting in hysteresis synchronous motors utilized to drive optical scanners by controlling the frequency of the drive signal applied to the motor. A laser beam is reflected from the facets of the optical scanner and scans a surface along a scan line, a signal being generated at the start and end of each scan line. A counter is driven by an accurate clock which is started and stopped in accordance with the start and end of scan signals. The resulting count of the counter is thus inversely proportional to the speed of the motor and is converted to an analog input signal and coupled to a voltage controlled oscillator whose frequency is controlled for driving the motor such that undesirable oscillations of the motor are damped out. Additional embodiments for controlling the motor speed are disclosed which utilize only the start of scan signal to both start and stop the counter.