Patents by Inventor William F. Jones

William F. Jones has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190386334
    Abstract: The present invention relates to the application of a force to enhance the performance of an electrochemical cell. The force may comprise, in some instances, an anisotropic force with a component normal to an active surface of the anode of the electrochemical cell. In the embodiments described herein, electrochemical cells (e.g., rechargeable batteries) may undergo a charge/discharge cycle involving deposition of metal (e.g., lithium metal) on a surface of the anode upon charging and reaction of the metal on the anode surface, wherein the metal diffuses from the anode surface, upon discharging. The uniformity with which the metal is deposited on the anode may affect cell performance. For example, when lithium metal is redeposited on an anode, it may, in some cases, deposit unevenly forming a rough surface. The roughened surface may increase the amount of lithium metal available for undesired chemical reactions which may result in decreased cycling lifetime and/or poor cell performance.
    Type: Application
    Filed: April 22, 2019
    Publication date: December 19, 2019
    Applicant: Sion Power Corporation
    Inventors: Chariclea Scordilis-Kelley, John D. Affinito, Lowell D. Jones, Yuriy V. Mikhaylik, Igor P. Kovalev, William F. Wilkening, Christopher T. S. Campbell, John A. Martens
  • Publication number: 20190228810
    Abstract: Apparatuses and methods for targeted row refreshes are disclosed herein. In an example apparatus, a predecoder receives a target row address and determines whether a target row of memory associated with the target row address is a primary or a redundant row of memory. The predecoder is further configured to cause one or more rows of memory physically adjacent the primary row of memory to be refreshed if the primary row is the target row or one or more rows of memory physically adjacent the redundant row of memory to be refreshed if the redundant row of memory is the target row of memory.
    Type: Application
    Filed: April 4, 2019
    Publication date: July 25, 2019
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: William F. Jones, Jeffrey P. Wright
  • Patent number: 10320027
    Abstract: The present invention relates to the application of a force to enhance the performance of an electrochemical cell. The force may comprise, in some instances, an anisotropic force with a component normal to an active surface of the anode of the electrochemical cell. In the embodiments described herein, electrochemical cells (e.g., rechargeable batteries) may undergo a charge/discharge cycle involving deposition of metal (e.g., lithium metal) on a surface of the anode upon charging and reaction of the metal on the anode surface, wherein the metal diffuses from the anode surface, upon discharging. The uniformity with which the metal is deposited on the anode may affect cell performance. For example, when lithium metal is redeposited on an anode, it may, in some cases, deposit unevenly forming a rough surface. The roughened surface may increase the amount of lithium metal available for undesired chemical reactions which may result in decreased cycling lifetime and/or poor cell performance.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: June 11, 2019
    Assignee: Sion Power Corporation
    Inventors: Chariclea Scordilis-Kelley, John D. Affinito, Lowell D. Jones, Yuriy V. Mikhaylik, Igor P. Kovalev, William F. Wilkening, Christopher T. S. Campbell, John A. Martens
  • Patent number: 10312545
    Abstract: The present invention relates to the application of a force to enhance the performance of an electrochemical cell. The force may comprise, in some instances, an anisotropic force with a component normal to an active surface of the anode of the electrochemical cell. In the embodiments described herein, electrochemical cells (e.g., rechargeable batteries) may undergo a charge/discharge cycle involving deposition of metal (e.g., lithium metal) on a surface of the anode upon charging and reaction of the metal on the anode surface, wherein the metal diffuses from the anode surface, upon discharging. The uniformity with which the metal is deposited on the anode may affect cell performance. For example, when lithium metal is redeposited on an anode, it may, in some cases, deposit unevenly forming a rough surface. The roughened surface may increase the amount of lithium metal available for undesired chemical reactions which may result in decreased cycling lifetime and/or poor cell performance.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: June 4, 2019
    Assignee: Sion Power Corporation
    Inventors: Chariclea Scordilis-Kelley, John D. Affinito, Lowell D. Jones, Yuriy V. Mikhaylik, Igor P. Kovalev, William F. Wilkening, Christopher T. S. Campbell, John A. Martens
  • Publication number: 20190103147
    Abstract: Apparatuses and methods for targeted row refreshes are disclosed herein. In an example apparatus, a predecoder receives a target row address and determines whether a target row of memory associated with the target row address is a primary or a redundant row of memory. The predecoder is further configured to cause one or more rows of memory physically adjacent the primary row of memory to be refreshed if the primary row is the target row or one or more rows of memory physically adjacent the redundant row of memory to be refreshed if the redundant row of memory is the target row of memory.
    Type: Application
    Filed: November 14, 2018
    Publication date: April 4, 2019
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: William F. Jones, Jeffrey P. Wright
  • Patent number: 10147472
    Abstract: Apparatuses and methods for targeted row refreshes are disclosed herein. In an example apparatus, a predecoder receives a target row address and determines whether a target row of memory associated with the target row address is a primary or a redundant row of memory. The predecoder is further configured to cause one or more rows of memory physically adjacent the primary row of memory to be refreshed if the primary row is the target row or one or more rows of memory physically adjacent the redundant row of memory to be refreshed if the redundant row of memory is the target row of memory.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: December 4, 2018
    Assignee: Micron Technology, Inc.
    Inventors: William F. Jones, Jeffrey P. Wright
  • Publication number: 20170323675
    Abstract: Apparatuses and methods for targeted row refreshes are disclosed herein. In an example apparatus, a predecoder receives a target row address and determines whether a target row of memory associated with the target row address is a primary or a redundant row of memory. The predecoder is further configured to cause one or more rows of memory physically adjacent the primary row of memory to be refreshed if the primary row is the target row or one or more rows of memory physically adjacent the redundant row of memory to be refreshed if the redundant row of memory is the target row of memory.
    Type: Application
    Filed: July 21, 2017
    Publication date: November 9, 2017
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: William F. Jones, Jeffrey P. Wright
  • Patent number: 9741409
    Abstract: Apparatuses and methods for targeted row refreshes are disclosed herein. In an example apparatus, a predecoder receives a target row address and determines whether a target row of memory associated with the target row address is a primary or a redundant row of memory. The predecoder is further configured to cause one or more rows of memory physically adjacent the primary row of memory to be refreshed if the primary row is the target row or one or more rows of memory physically adjacent the redundant row of memory to be refreshed if the redundant row of memory is the target row of memory.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: August 22, 2017
    Assignee: Micron Technology, Inc.
    Inventors: William F. Jones, Jeffrey P. Wright
  • Patent number: 9508409
    Abstract: Apparatuses and methods for implementing masked write commands are disclosed herein. An example apparatus may include a memory bank, a local buffer circuit, and an address control circuit. The local buffer circuit may be associated with the memory bank. The address control circuit may be coupled to the memory bank and configured to receive a command and an address associated with the command. The address control circuit may include a global buffer circuit configured to store the address. The address control circuit may further be configured to delay the command using one of a plurality of command paths based, at least in part, on a write latency and to provide the address stored in the global buffer circuit to the local buffer circuit to be stored therein.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: November 29, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Mark K. Hadrick, Jeffrey P. Wright, Victor Wong, Simon J. Lovett, Donald M. Morgan, William F. Jones, Sujeet Ayyapureddi, Dean D. Gans, Jongtae Kwak
  • Patent number: 9444297
    Abstract: A method of spacing a plurality of electrical conductors for carrying electrical current in an electrical machine may include positioning between the electrical conductors an uncured spacer body. The uncured spacer body may include a curable material, and an activatable heat generating material mixed with the curable material. The method may further include activating the activatable heat generating material to heat the curable material to form a cured spacer to thereby space the electrical conductors in the electrical machine.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: September 13, 2016
    Assignee: SIEMENS ENERGY, INC.
    Inventor: William F. Jones
  • Patent number: 9324398
    Abstract: Apparatuses and methods for targeted row refreshes are disclosed herein. In an example apparatus, a predecoder receives a target row address and determines whether a target row of memory associated with the target row address is a primary or a redundant row of memory. The predecoder is further configured to cause one or more rows of memory physically adjacent the primary row of memory to be refreshed if the primary row is the target row or one or more rows of memory physically adjacent the redundant row of memory to be refreshed if the redundant row of memory is the target row of memory.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: April 26, 2016
    Assignee: Micron Technology, Inc.
    Inventors: William F. Jones, Jeffrey P. Wright
  • Publication number: 20160027531
    Abstract: Apparatuses and methods for targeted row refreshes are disclosed herein. In an example apparatus, a predecoder receives a target row address and determines whether a target row of memory associated with the target row address is a primary or a redundant row of memory. The predecoder is further configured to cause one or more rows of memory physically adjacent the primary row of memory to be refreshed if the primary row is the target row or one or more rows of memory physically adjacent the redundant row of memory to be refreshed if the redundant row of memory is the target row of memory.
    Type: Application
    Filed: October 8, 2015
    Publication date: January 28, 2016
    Inventors: WILLIAM F. JONES, JEFFREY P. WRIGHT
  • Publication number: 20150302907
    Abstract: Apparatuses and methods for implementing masked write commands are disclosed herein. An example apparatus may include a memory bank, a local buffer circuit, and an address control circuit. The local buffer circuit may be associated with the memory bank. The address control circuit may be coupled to the memory bank and configured to receive a command and an address associated with the command. The address control circuit may include a global buffer circuit configured to store the address. The address control circuit may further be configured to delay the command using one of a plurality of command paths based, at least in part, on a write latency and to provide the address stored in the global buffer circuit to the local buffer circuit to be stored therein.
    Type: Application
    Filed: April 16, 2014
    Publication date: October 22, 2015
    Applicant: Micron Technology, Inc.
    Inventors: Mark K. Hadrick, Jeffrey P. Wright, Victor Wong, Simon J. Lovett, Donald M. Morgan, William F. Jones, Sujeet Ayyapureddi, Dean D. Gans, Jongtae Kwak
  • Patent number: 8942054
    Abstract: Memories, systems, and methods for refreshing are provided, such as a memory with an array of memory cells divided into sections. Memories include replacement elements having a digit line, and detecting circuitry coupled to a digit line of at least one section of the memory cell array and coupled to the digit line of the replacement element. Memories include control logic configured to selectively refresh the replacement element at an occurrence when a non-neighboring section of the memory cell array relative to the replacement element is refreshed. Other memories, systems, and methods are provided.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: January 27, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Victor Wong, William F. Jones, Seth A. Eichmeyer
  • Publication number: 20140219043
    Abstract: Apparatuses and methods for targeted row refreshes are disclosed herein. In an example apparatus, a predecoder receives a target row address and determines whether a target row of memory associated with the target row address is a primary or a redundant row of memory. The predecoder is further configured to cause one or more rows of memory physically adjacent the primary row of memory to be refreshed if the primary row is the target row or one or more rows of memory physically adjacent the redundant row of memory to be refreshed if the redundant row of memory is the target row of memory.
    Type: Application
    Filed: February 4, 2013
    Publication date: August 7, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: William F. Jones, Jeffrey P. Wright
  • Publication number: 20140145546
    Abstract: A method of spacing a plurality of electrical conductors for carrying electrical current in an electrical machine may include positioning between the electrical conductors an uncured spacer body. The uncured spacer body may include a curable material, and an activatable heat generating material mixed with the curable material. The method may further include activating the activatable heat generating material to heat the curable material to form a cured spacer to thereby space the electrical conductors in the electrical machine.
    Type: Application
    Filed: January 31, 2014
    Publication date: May 29, 2014
    Applicant: Siemens Energy, Inc.
    Inventor: William F. Jones
  • Patent number: 8641855
    Abstract: A method of spacing a plurality of electrical conductors for carrying electrical current in an electrical machine may include positioning between the electrical conductors an uncured spacer body. The uncured spacer body may include a curable material, and an activatable heat generating material mixed with the curable material. The method may further include activating the activatable heat generating material to heat the curable material to form a cured spacer to thereby space the electrical conductors in the electrical machine.
    Type: Grant
    Filed: August 8, 2008
    Date of Patent: February 4, 2014
    Assignee: Siemens Energy, Inc.
    Inventor: William F. Jones
  • Patent number: 8314380
    Abstract: A patient bed drive mechanism, under control of a processor, is capable of continuously moving a patient bed through the a TOF-PET detector array having a stationary field of view (FOV) for a distance in excess of the physical extent of an axis of the array FOV. A direct memory access (DMA) rebinner card is coupled to the detector array to receive therefrom a stream of TOF-PET coincidence event data during the extent of movement of the bed. Image projection data are generated in real time from the acquired stream of TOF-PET coincidence event data via the DMA card.
    Type: Grant
    Filed: September 11, 2009
    Date of Patent: November 20, 2012
    Assignee: Siemens Medical Solutions USA, Inc.
    Inventors: John E. Breeding, William F. Jones, Wing K. Luk, Andrew P. Moor, Johnny H. Reed, David Townsend
  • Patent number: 8298480
    Abstract: A method of manufacturing specialized alloys having specific properties and an alloy made using this method. The methods involve the use of micro and/or nano-sized particles that are mixed into an alloy using a friction stir welding method. The micro and/or nano-sized particles are used to alter one or more characteristics of the alloy in the locations in which the micro and/or nano-sized particles are added. The micro and/or nano-sized particles may be metal particles, non-metal particles, or a combination thereof.
    Type: Grant
    Filed: March 16, 2005
    Date of Patent: October 30, 2012
    Assignee: Siemens Energy, Inc.
    Inventors: William F. Jones, Srikanth C. Kottilingam
  • Publication number: 20120263001
    Abstract: Memories, systems, and methods for refreshing are provided, such as a memory with an array of memory cells divided into sections. Memories include replacement elements having a digit line, and detecting circuitry coupled to a digit line of at least one section of the memory cell array and coupled to the digit line of the replacement element. Memories include control logic configured to selectively refresh the replacement element at an occurrence when a non-neighboring section of the memory cell array relative to the replacement element is refreshed. Other memories, systems, and methods are provided.
    Type: Application
    Filed: June 25, 2012
    Publication date: October 18, 2012
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Victor Wong, William F. Jones, Seth A. Eichmeyer