Abstract: In one embodiment, a system is configured to generate a time reference where the system includes a bi-directional loop configured to have a first propagation speed in a first direction and a second propagation speed in a second direction, wherein the first propagation speed is substantially equal to the second propagation speed. In one embodiment, the system further includes a plurality of system elements coupled to the bi-directional loop, wherein each respective system element of the plurality of system elements is configured to determine a time reference common to each as an average arrival time at the respective system element of a first signal transmitted in the first direction over the bi-directional loop and a second signal transmitted in the second direction over the bi-directional loop.

Abstract: A waveform generation and measurement module that may be used in automated test equipment. The waveform generation and measurement module includes high speed SERDES (or other shift registers) that are used to digitally draw a test waveform. Additional high speed SERDES may also be used to receive (in serial form) a response waveform from a device under test and convert it to parallel data for high speed processing. The waveform generation and measurement module may be implemented in field programmable gate array logic.

Abstract: In one embodiment, a system is configured to generate a time reference where the system includes a bi-directional loop configured to have a first propagation speed in a first direction and a second propagation speed in a second direction, wherein the first propagation speed is substantially equal to the second propagation speed. In one embodiment, the system further includes a plurality of system elements coupled to the bi-directional loop, wherein each respective system element of the plurality of system elements is configured to determine a time reference common to each as an average arrival time at the respective system element of a first signal transmitted in the first direction over the bi-directional loop and a second signal transmitted in the second direction over the bi-directional loop.

Abstract: A waveform generation and measurement module that may be used in automated test equipment. The waveform generation and measurement module includes high speed SERDES (or other shift registers) that are used to digitally draw a test waveform. Additional high speed SERDES may also be used to receive (in serial form) a response waveform from a device under test and convert it to parallel data for high speed processing. The waveform generation and measurement module may be implemented in field programmable gate array logic.

Abstract: A waveform generation and measurement module that may be used in automated test equipment. The waveform generation and measurement module includes high speed SERDES (or other shift registers) that are used to digitally draw a test waveform. Additional high speed SERDES may also be used to receive (in serial form) a response waveform from a device under test and convert it to parallel data for high speed processing. The waveform generation and measurement module may be implemented in field programmable gate array logic.

Abstract: In one embodiment, a system is configured to generate a time reference where the system includes a bi-directional loop configured to have a first propagation speed in a first direction and a second propagation speed in a second direction, wherein the first propagation speed is substantially equal to the second propagation speed. In one embodiment, the system further includes a plurality of system elements coupled to the bi-directional loop, wherein each respective system element of the plurality of system elements is configured to determine a time reference common to each as an average arrival time at the respective system element of a first signal transmitted in the first direction over the bi-directional loop and a second signal transmitted in the second direction over the bi-directional loop.

Abstract: A waveform generation and measurement module that may be used in automated test equipment. The waveform generation and measurement module includes high speed SERDES (or other shift registers) that are used to digitally draw a test waveform. Additional high speed SERDES may also be used to receive (in serial form) a response waveform from a device under test and convert it to parallel data for high speed processing. The waveform generation and measurement module may be implemented in field programmable gate array logic.

Abstract: An improved hardware modeling system that is preferably embodied as a stand-alone system for networked connection to one or a variety of host computers that are used to design digital electronics systems, the hardware modeling system having a network interface for communicating between the hardware modeling system and the host computer, a central processing unit for controlling operation of the hardware modeling system, a central timing unit for generating timing signals for use in the operation of the hardware modeling system including the generation of precision clocks, data formatting strobes and sample strobes, an internal pattern bus for transmission of read/write requests from the central processing unit in one operational mode and pattern sequences for stimulation of the hardware modeling element in a second operational mode, a pattern controller for controlling presentation and delivery of the pattern sequences to the pattern bus, a pattern memory connected to the pattern controller for storing stimul

Abstract: An improved system for and method of connecting a hardware modeling element to the pin electronics circuitry of a hardware modeling system, with the improved system having circuitry and structures that will allow it to be connected to a hardware modeling system that is powered, circuitry to indicate to the pin electronics circuitry that the improved system is connected to it, circuitry to identify the hardware modeling element supported by the improved system to the hardware modeling system, circuitry to indicate to the hardware modeling system when the hardware modeling element is initialized so evaluation of it by the hardware modeling system can commence, circuitry to generate selectable supply voltages for the powering the hardware modeling element, and a hardware modeling element connector that will allow the connection of a family of hardware modeling elements to the same connector without the need to change the connector.

Abstract: An improved hardware modeling system that is preferably embodied as a stand-alone system for networked connection to one or a variety of host computers that are used to design digital electronics systems, the hardware modeling system having a network interface for communicating between the hardware modeling system and the host computer, a central processing unit for controlling operation of the hardware modeling system, a central timing unit for generating timing signals for use in the operation of the hardware modeling system including the generation of precision clocks, data formatting strobes and sample strobes, an internal pattern bus for transmission of read/write requests from the central processing unit in one operational mode and pattern sequences for stimulation of the hardware modeling element in a second operational mode, a pattern controller for controlling presentation and delivery of the pattern sequences to the pattern bus, a pattern memory connected to the pattern controller for storing stimul