Patents by Inventor William F. Landers
William F. Landers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9490197Abstract: A three-dimensional organic structure or glass interposer structure and methods of manufacture are disclosed. The method includes forming lined metal vias in a substrate. The method further includes removing the substrate, leaving the lined metal vias. The method further includes forming a new substrate about the lined metal vias. The method also includes connecting the lined metal vias to wiring layers using back end of the line processes.Type: GrantFiled: November 14, 2014Date of Patent: November 8, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Mukta G. Farooq, William F. Landers, Jin Liu, Andrew J. Martin, Kathryn E. Schlichting, Melissa A. Smith
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Publication number: 20160141237Abstract: A three-dimensional organic structure or glass interposer structure and methods of manufacture are disclosed. The method includes forming lined metal vias in a substrate. The method further includes removing the substrate, leaving the lined metal vias. The method further includes forming a new substrate about the lined metal vias. The method also includes connecting the lined metal vias to wiring layers using back end of the line processes.Type: ApplicationFiled: November 14, 2014Publication date: May 19, 2016Inventors: Mukta G. FAROOQ, William F. LANDERS, Jin LIU, Andrew J. MARTIN, Kathryn E. SCHLICHTING, Melissa A. SMITH
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Patent number: 9059167Abstract: The present invention relates to bonded semiconductor integrated circuits, more specifically to a structure to protect against crack propagation into any layer of such integrated circuits. Embodiments of the present invention may include a first semiconductor substrate having a first layer bonded to second layer of a substantially thinner second semiconductor substrate by a bonding layer. The first layer may contain a crack stop. The crack stop may be in contact with a circumferential wall, made up of posts, that extends through the bonding layer, the second layer, and the second substrate.Type: GrantFiled: July 31, 2014Date of Patent: June 16, 2015Assignee: International Business Machines CorporationInventors: Mukta G. Farooq, John A. Griesemer, William F. Landers, Ian D. Melville, Thomas M. Shaw, Huilong Zhu
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Publication number: 20140339703Abstract: A structure to prevent propagation of a crack into the active region of a 3D integrated circuit, such as a crack initiated by a flaw at the periphery of a thinned substrate layer or a bonding layer, and methods of forming the same is disclosed.Type: ApplicationFiled: July 31, 2014Publication date: November 20, 2014Inventors: Mukta G. Farooq, John A. Griesemer, William F. Landers, Ian D. Melville, Thomas M. Shaw, Huilong Zhu
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Patent number: 8859390Abstract: A structure to prevent propagation of a crack into the active region of a 3D integrated circuit, such as a crack initiated by a flaw at the periphery of a thinned substrate layer or a bonding layer, and methods of forming the same is disclosed.Type: GrantFiled: February 5, 2010Date of Patent: October 14, 2014Assignee: International Business Machines CorporationInventors: Mukta G Farooq, John A Griesemer, William F Landers, Ian D Melville, Thomas M Shaw, Huilong Zhu
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Patent number: 8691691Abstract: The present invention includes embodiments of a processing method, and resulting structure, for building a chip having a TSV pillar which can be used as an interconnecting structure. The process includes the deposition of a dual diffusion barrier between the TSV and the substrate the TSV is embedded within. The TSV is then exposed from the back side of the substrate so that at least a portion of the TSV protrudes from the substrate and can be used as a contact for connecting the chip to another surface. The resulting TSV is rigid, highly conductive, can be placed in a tightly pitched grid of contacts, and reduces effects of CTE mismatch.Type: GrantFiled: July 29, 2011Date of Patent: April 8, 2014Assignee: International Business Machines CorporationInventors: Mukta G. Farooq, Troy L. Graves-Abe, William F. Landers, Kevin S. Petrarca, Richard P. Volant
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Patent number: 8546961Abstract: Disclosed are a structure including alignment marks and a method of forming alignment marks in three dimensional (3D) structures. The method includes forming apertures in a first surface of a first semiconductor substrate; joining the first surface of the first semiconductor substrate to a first surface of a second semiconductor substrate; thinning the first semiconductor on a second surface of the first semiconductor substrate to provide optical contrast between the apertures and the first semiconductor substrate; and aligning a feature on the second surface of the first semiconductor substrate using the apertures as at least one alignment mark.Type: GrantFiled: January 10, 2011Date of Patent: October 1, 2013Assignee: International Business Machines CorporationInventors: Mukta G. Farooq, Troy L. Graves-Abe, Robert Hannon, Emily R. Kinser, William F. Landers, Kevin S. Petrarca, Richard P. Volant, Kevin R. Winstel
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Publication number: 20130026606Abstract: The present invention includes embodiments of a processing method, and resulting structure, for building a chip having a TSV pillar which can be used as an interconnecting structure. The process includes the deposition of a dual diffusion barrier between the TSV and the substrate the TSV is embedded within. The TSV is then exposed from the back side of the substrate so that at least a portion of the TSV protrudes from the substrate and can be used as a contact for connecting the chip to another surface. The resulting TSV is rigid, highly conductive, can be placed in a tightly pitched grid of contacts, and reduces effects of CTE mismatch.Type: ApplicationFiled: July 29, 2011Publication date: January 31, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mukta G. Farooq, Troy L. Graves-Abe, William F. Landers, Kevin S. Petrarca, Richard P. Volant
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Publication number: 20120175789Abstract: Disclosed are a structure including alignment marks and a method of forming alignment marks in three dimensional (3D) structures. The method includes forming apertures in a first surface of a first semiconductor substrate; joining the first surface of the first semiconductor substrate to a first surface of a second semiconductor substrate; thinning the first semiconductor on a second surface of the first semiconductor substrate to provide optical contrast between the apertures and the first semiconductor substrate; and aligning a feature on the second surface of the first semiconductor substrate using the apertures as at least one alignment mark.Type: ApplicationFiled: January 10, 2011Publication date: July 12, 2012Applicant: International Business Machines CorporationInventors: Mukta G. Farooq, Troy L. Graves-Abe, Robert Hannon, Emily R. Kinser, William F. Landers, Kevin S. Patrarca, Richard P. Volant, Kevin R. Winstel
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Publication number: 20110193197Abstract: A structure to prevent propagation of a crack into the active region of a 3D integrated circuit, such as a crack initiated by a flaw at the periphery of a thinned substrate layer or a bonding layer, and methods of forming the same is disclosed.Type: ApplicationFiled: February 5, 2010Publication date: August 11, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: MUKTA G. FAROOQ, JOHN A. GRIESEMER, WILLIAM F. LANDERS, IAN D. MELVILLE, THOMAS M. SHAW, HUILONG ZHU
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Patent number: 7863183Abstract: The present invention relates to a method for fabricating a semiconductor device with a last level copper-to-C4 connection that is essentially free of aluminum. Specifically, the last level copper-to-C4 connection comprises an interfacial cap structure containing CoWP, NiMoP, NiMoB, NiReP, NiWP, and combinations thereof. Preferably, the interfacial cap structure comprises at least one CoWP layer. Such a CoWP layer can be readily formed over a last level copper interconnect by a selective electroless plating process.Type: GrantFiled: January 18, 2006Date of Patent: January 4, 2011Assignee: International Business Machines CorporationInventors: Timothy H. Daubenspeck, William F. Landers, Donna S. Zupanski-Nielsen
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Patent number: 7678673Abstract: The present invention provides a method of strengthening a structure, to heal the imperfection of the structure, to reinforce the structure, and thus strengthening the dielectric without compromising the desirable low dielectric constant of the structure. The inventive method includes the steps of providing a semiconductor structure having at least one interconnect structure; dicing the interconnect structure; applying at least one infiltrant into the interconnect structure; and infiltrating the infiltrant to infiltrate into the interconnect structure.Type: GrantFiled: August 1, 2007Date of Patent: March 16, 2010Assignee: International Business Machines CorporationInventors: Elbert Huang, William F. Landers, Michael Lane, Eric G. Liniger, Xiao H. Liu, David L. Questad, Thomas M. Shaw
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Patent number: 7544602Abstract: An integrated circuit design and a method of fabrication and, more particularly, a semiconductor structure having an ultra narrow crack stop for use in multilevel level devices and a method of making the same. The structure includes a first dielectric layer having a first connection connecting to an underlying interconnect and a second dielectric layer having a second connection connecting to the first connection. A stop gap structure extends through the first dielectric layer and the second dielectric layer, and has a width of about less than 1 um.Type: GrantFiled: March 29, 2007Date of Patent: June 9, 2009Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Matthew E. Colburn, William F. Landers, Wai-Kin Li
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Publication number: 20090035480Abstract: The present invention provides a method of strengthening a structure, to heal the imperfection of the structure, to reinforce the structure, and thus strengthening the dielectric without compromising the desirable low dielectric constant of the structure. The inventive method includes the steps of providing a semiconductor structure having at least one interconnect structure; dicing the interconnect structure; applying at least one infiltrant into the interconnect structure; and infiltrating the infiltrant to infiltrate into the interconnect structure.Type: ApplicationFiled: August 1, 2007Publication date: February 5, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Elbert Huang, William F. Landers, Michael Lane, Eric G. Liniger, Xiao H. Liu, David L. Questad, Thomas M. Shaw
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Publication number: 20080237868Abstract: An integrated circuit design and a method of fabrication and, more particularly, a semiconductor structure having an ultra narrow crack stop for use in multilevel level devices and a method of making the same. The structure includes a first dielectric layer having a first connection connecting to an underlying interconnect and a second dielectric layer having a second connection connecting to the first connection. A stop gap structure extends through the first dielectric layer and the second dielectric layer, and has a width of about less than 1 um.Type: ApplicationFiled: March 29, 2007Publication date: October 2, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence A. Clevenger, Matthew E. Colburn, William F. Landers, Wai-Kin LI
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Patent number: 7312529Abstract: An electrical structure and method comprising a first substrate electrically and mechanically connected to a second substrate. The first substrate comprises a first electrically conductive pad and a second electrically conductive pad. The second substrate comprises a third electrically conductive pad, a fourth electrically conductive pad, and a first electrically conductive member. The fourth electrically conductive pad comprises a height that is different than a height of the first electrically conductive member. The electrically conductive member is electrically and mechanically connected to the fourth electrically conductive pad. A first solder ball connects the first electrically conductive pad to the third electrically conductive pad. The first solder ball comprises a first diameter. A second solder ball connects the second electrically conductive pad to the first electrically conductive member. The second solder ball comprises a second diameter. The first diameter is greater than said second diameter.Type: GrantFiled: July 5, 2005Date of Patent: December 25, 2007Assignee: International Business Machines CorporationInventors: Lawrence Clevenger, Mukta G. Farooq, Louis L. Hsu, William F. Landers, Donna S. Zupanski-Nielsen, Carl J. Radens, Chih-Chao Yang
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Patent number: 7294565Abstract: A method for sealing an exposed surface of a wire bond pad with a material that is capable of preventing a possible chemical attack during electroless deposition of Ni/Au pad metallurgy is provided. Specifically, the present invention provides a method whereby a TiN/Ti or TiN/Al cap is used as a protective coating covering exposed surfaces of a wire bond pad. The TiN/Ti or TiN/Al cap is not affected by alkaline chemistries used in forming the Ni/Au metallization, yet it provides a sufficient electrical pathway connecting the bond pads to the Ni/Au pad metallization.Type: GrantFiled: October 1, 2003Date of Patent: November 13, 2007Assignee: International Business Machines CorporationInventors: Lloyd G. Burrell, Charles R. Davis, Ronald D. Goldblatt, William F. Landers, Sanjay C. Mehta
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Publication number: 20070166992Abstract: The present invention relates to a method for fabricating a semiconductor device with a last level copper-to-C4 connection that is essentially free of aluminum. Specifically, the last level copper-to-C4 connection comprises an interfacial cap structure containing CoWP, NiMoP, NiMoB, NiReP, NiWP, and combinations thereof. Preferably, the interfacial cap structure comprises at least one CoWP layer. Such a CoWP layer can be readily formed over a last level copper interconnect by a selective electroless plating process.Type: ApplicationFiled: January 18, 2006Publication date: July 19, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy H. Daubenspeck, William F. Landers, Donna S. Zupanski-Nielsen
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Patent number: 7098676Abstract: An on-chip redundant crack termination barrier structure, or crackstop, provides a barrier for preventing defects, cracks, delaminations, and moisture/oxidation contaminants from reaching active circuit regions. Conductive materials in the barrier structure design permits wiring the barriers out to contact pads and device pins for coupling a monitor device to the chip for monitoring barrier integrity.Type: GrantFiled: January 8, 2003Date of Patent: August 29, 2006Assignee: International Business Machines CorporationInventors: William F. Landers, Thomas M. Shaw, Diana Llera-Hurlburt, Scott W. Crowder, Vincent J. McGahay, Sandra G. Malhotra, Charles R. Davis, Ronald D. Goldblatt, Brett H. Engel
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Patent number: 6815346Abstract: A mesh-like reinforcing structure to inhibit delamination and cracking is fabricated in a multilayer semiconductor device using low-k dielectric materials and copper-based metallurgy. The mesh-like interconnection structure comprises conductive pads interconnected by conductive lines at each wiring level with each pad conductively connected to its adjacent pad at the next wiring level by a plurality of conductive vias. The conductive pads, lines and vias are fabricated during the normal BEOL wiring level integration process. The reinforcing structure provides both vertical and horizontal reinforcement and may be fabricated on the periphery of the active device region or within open regions of the device that are susceptible to delamination and cracking.Type: GrantFiled: May 13, 2003Date of Patent: November 9, 2004Assignee: International Business Machines CorporationInventors: Charles R. Davis, David L. Hawken, Dae Young Jung, William F. Landers, David L. Questad