Patents by Inventor William F. Shutler
William F. Shutler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6974722Abstract: A jogging structure for translating wiring connections from points in a first grid to corresponding points in a second grid in a chip carrier module is disclosed. In an exemplary embodiment, the structure includes a first translation layer, coupled to the first grid, the first translation layer translating the first grid in an x-axis direction. A second translation layer is coupled to the first translation layer, the second translation layer for translating said wiring connections from the first grid in a y-axis direction, the y-axis direction being orthogonal to the x-axis direction. The second translation layer is further coupled to the second grid.Type: GrantFiled: April 7, 2004Date of Patent: December 13, 2005Assignee: International Business Machines CorporationInventors: Glenn G. Daves, Jason Frankel, William F. Shutler, Anthony Wayne Sigler, Herbert I. Stoller, John Vetrero, Cathy Ann Zadany
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Publication number: 20040188823Abstract: A jogging structure for translating wiring connections from points in a first grid to corresponding points in a second grid in a chip carrier module is disclosed. In an exemplary embodiment, the structure includes a first translation layer, coupled to the first grid, the first translation layer translating the first grid in an x-axis direction. A second translation layer is coupled to the first translation layer, the second translation layer for translating said wiring connections from the first grid in a y-axis direction, the y-axis direction being orthogonal to the x-axis direction. The second translation layer is further coupled to the second grid.Type: ApplicationFiled: April 7, 2004Publication date: September 30, 2004Applicant: International Business Machines CorporationInventors: Glenn G. Daves, Jason Frankel, William F. Shutler, Anthony Wayne Sigler, Herbert I. Stoller, John Vetrero, Cathy Ann Zadany
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Patent number: 6762489Abstract: A jogging structure for translating wiring connections from points in a first grid to corresponding points in a second grid in a chip carrier module is disclosed. In an exemplary embodiment, the structure includes a first translation layer, coupled to the first grid, the first translation layer translating the first grid in an x-axis direction. A second translation layer is coupled to the first translation layer, the second translation layer for translating said wiring connections from the first grid in a y-axis direction, the y-axis direction being orthogonal to the x-axis direction. The second translation layer is further coupled to the second grid.Type: GrantFiled: November 20, 2001Date of Patent: July 13, 2004Assignee: International Business Machines CorporationInventors: Glenn G. Daves, Jason Frankel, William F. Shutler, Anthony Wayne Sigler, Herbert I. Stoller, John Vetrero, Cathy Ann Zadany
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Publication number: 20030094687Abstract: A jogging structure for translating wiring connections from points in a first grid to corresponding points in a second grid in a chip carrier module is disclosed. In an exemplary embodiment, the structure includes a first translation layer, coupled to the first grid, the first translation layer translating the first grid in an x-axis direction. A second translation layer is coupled to the first translation layer, the second translation layer for translating said wiring connections from the first grid in a y-axis direction, the y-axis direction being orthogonal to the x-axis direction. The second translation layer is further coupled to the second grid.Type: ApplicationFiled: November 20, 2001Publication date: May 22, 2003Inventors: Glenn G. Daves, Jason Frankel, William F. Shutler, Anthony Wayne Sigler, Herbert I. Stoller, John Vetrero, Cathy Ann Zadany
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Patent number: 6469375Abstract: A three-dimensional memory module in a repetitively used pedestal connector provides signal paths unique and common to the module at its level and signal paths from the level below unique to and common to modules at levels above. In order to provide a unique signal path from a substrate to each memory module, while using identical pedestal connectors at each level, signal lines are skewed from where they enter the bottom surface of the pedestal connector to where they exit the top surface. For example, each input in a line of inputs is connected to a matching line of outputs, but with a shift of one position between input and output.Type: GrantFiled: February 28, 2001Date of Patent: October 22, 2002Inventors: William F. Beausoleil, Edmund D. Blackshear, Michael J. Ellsworth, Jr., William F. Shutler, Norton J. Tomassetti
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Publication number: 20020117741Abstract: A three-dimensional memory module in a repetitively used pedestal connector provides signal paths unique and common to the module at its level and signal paths from the level below unique to and common to modules at levels above. In order to provide a unique signal path from a substrate to each memory module, while using identical pedestal connectors at each level, signal lines are skewed from where they enter the bottom surface of the pedestal connector to where they exit the top surface. For example, each input in a line of inputs is connected to a matching line of outputs, but with a shift of one position between input and output.Type: ApplicationFiled: February 28, 2001Publication date: August 29, 2002Inventors: William F. Beausoleil, Edmund D. Blackshear, Michael J. Ellsworth, William F. Shutler, Norton J. Tomassetti
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Patent number: 6442041Abstract: Disclosed is a multilayer electronics packaging structure, especially for use in a multi chip module. By forming an overlap of signal conductors by the respective mesh conductors, an improved shielding effect is achieved and coupling between signal conductors is reduced. By increasing the via punch pitch such that multiple wiring channels are formed between adjacent vias, wirability is improved and the number of signal distribution layers may be reduced. The new structure thus shows improved electrical properties over the state-of-the-art structures, combined with a cost reduction of about 35%.Type: GrantFiled: December 19, 2000Date of Patent: August 27, 2002Assignee: International Business Machines CorporationInventors: Simone Rehm, Bernd Garden, Erich Klink, Gisbert Thomke, William F. Shutler
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Publication number: 20010046125Abstract: Disclosed is a multilayer electronics packaging structure, especially for use in a multi chip module. By forming an overlap of signal conductors by the respective mesh conductors, an improved shielding effect is achieved and coupling between signal conductors is reduced. By increasing the via punch pitch such that multiple wiring channels are formed between adjacent vias, wirability is improved and the number of signal distribution layers may be reduced. The new structure thus shows improved electrical properties over the state-of-the-art structures, combined with a cost reduction of about 35%.Type: ApplicationFiled: December 19, 2000Publication date: November 29, 2001Applicant: International Business Machines CorporationInventors: Simone Rehm, Bernd Garben, Erich Klink, Gisbert Thomke, William F. Shutler
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Patent number: 6043724Abstract: Described is a novel implementation of a medium and high frequency on-module (off-chip)/on-chip power noise filter for power noise sensitive circuits. To achieve this, a second order low-pass approach is used. The first stage capacitor is located on-module (off-chip), and the second stage capacitor is implemented on-chip.Type: GrantFiled: January 29, 1998Date of Patent: March 28, 2000Assignee: International Business Machines CorporationInventors: Roland Frech, Erich Klink, William F. Shutler, Ulrich Weiss, Thomas-Michael Winkel
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Patent number: 5914533Abstract: The invention relates to a multilayer module 20 for packaging of at least one electronic component, such as the integrated circuit chips 21, 22. The module 20 comprises a thickfilm structure and a thinfilm structure. The thinfilm structure provides an interface between the electronic components and the thickfilm structure. The thinfilm structure comprises a first powerplane and a redistribution wiring structure. The topmost layer of conductors of the thickfilm structure is a second powerplane so that an electrical structure approaching a triplate structure is realized.Type: GrantFiled: January 10, 1997Date of Patent: June 22, 1999Assignee: International Business Machines CorporationInventors: Roland Frech, Hubert Harrer, Erich Klink, William F. Shutler
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Patent number: 5032897Abstract: A thermoelectrically cooled integrated circuit package including an insulative module which defines a cavity, a thermoelectric cooler within the cavity, and an integrated circuit chip connected to the thermoelectric cooler, thus providing an integrated circuit package in which the integrated circuit package itself dissipates thermal energy generated by the integrated circuit chip.Type: GrantFiled: February 28, 1990Date of Patent: July 16, 1991Assignee: International Business Machines Corp.Inventors: Mohanlal S. Mansuria, Joseph M. Mosley, Richard D. Musa, William F. Shutler, Vito J. Tuozzolo
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Patent number: 4718039Abstract: A dual ported buffer memory for a hierarchical memory, cmprising an addressable memory array for multi-bit words and a multi-bit register. Data is transferred a word at a time between the memory array and a multi-bit bus to a higher level in the memory system and between the memory array and the register. Data is transferred a bit at a time between the register and a single serial line. Concurrent operations are possible for transfers between the memory array and the parallel bus and between the register and the serial line.Type: GrantFiled: June 29, 1984Date of Patent: January 5, 1988Assignee: International Business MachinesInventors: Frederick J. Aichelmann, Jr., William F. Shutler, Vincent F. Sollitto, Jr.