Abstract: A latency controller within an integrated circuit device retimes command-stream-triggered control and timing signals into endpoint timing domains having respective time-varying phase offsets relative to a reference clock by iteratively estimating and logging the phase offsets independently of commands streaming into the integrated circuit device.

Abstract: In a memory controller having a controller core and a physical signaling interface, the controller core outputs a request for read data to the physical signaling interface specifying one of at least two memory components from which the read data is to be retrieved. In response to the request for read data, the physical signaling interface outputs a memory read request to the specified memory component, receives the read data from the specified memory component, and transfers the read data to the controller core at either a first time or a second time according to whether the specified memory component is a first memory component or second memory component of the at least two memory components.

Abstract: In a memory controller having a controller core and a physical signaling interface, the controller core outputs a request for read data to the physical signaling interface specifying one of at least two memory components from which the read data is to be retrieved. In response to the request for read data, the physical signaling interface outputs a memory read request to the specified memory component, receives the read data from the specified memory component, and transfers the read data to the controller core at either a first time or a second time according to whether the specified memory component is a first memory component or second memory component of the at least two memory components.

Abstract: A memory controller that extends the window when reading data from the memory device to compensate for fluctuations in a read strobe delay. The memory controller includes a communication port that receives a timing reference signal for reading data from a memory device. A control circuit generates a gating signal indicative of a read window. A gating adjustment circuit generates an adjusted gating signal indicative of an adjusted read window based on the gating signal and the timing reference signal. A gating circuit generates a first gated timing reference signal for reading data by gating a delayed version of the timing reference signal with the adjusted gating signal.

Abstract: A memory controller that extends the window when reading data from the memory device to compensate for fluctuations in a read strobe delay. The memory controller includes a communication port that receives a timing reference signal for reading data from a memory device. A control circuit generates a gating signal indicative of a read window. A gating adjustment circuit generates an adjusted gating signal indicative of an adjusted read window based on the gating signal and the timing reference signal. A gating circuit generates a first gated timing reference signal for reading data by gating a delayed version of the timing reference signal with the adjusted gating signal.

Abstract: An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (120), an analog voltage divider (104), an input comparator (125), a sampling latch (130), a current control counter (115), and a bitwise output driver (output driver A 107 and output driver B 111).

Abstract: Provided are a method and apparatus for high-speed, multi-mode PAM symbol transmission. A multi-mode PAM output driver drives one or more symbols, the number of levels used in the PAM modulation of the one or more symbols depending on the state of a PAM mode signal. Additionally, the one or more symbols are driven at a symbol rate, the symbol rate selected in accordance with the PAM mode signal so that a data rate of the driven symbols is constant with respect to changes in the state of the PAM mode signal. Further provided are methods for determining the optimal number of PAM levels for symbol transmission and reception in a given physical environment.

Abstract: A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization while maintaining the same output data latency. In one embodiment, this circuit is used on a bus-system to re-time data from receive-domain, clocks to transmit-domain clocks. In such a system the phase relationships between these two clocks is set by the device bus location and thus is not precisely known. By supporting arbitrary phase resynchronization, this disclosure allows for theoretically infinite bus-length and thus no limitation on device count, as well as arbitrary placement of devices along the bus. This ultimately allows support of multiple latency-domains for very long buses.

Abstract: A method of operating an integrated circuit including an output driver. The method includes storing a value in a register, wherein the value is representative of a voltage swing setting of an output driver. The voltage swing setting of the output driver is adjusted using a counter that holds a count value representing an update to the voltage swing setting. The count value is updated in accordance with a signal that indicates an adjustment to the voltage swing setting. In addition, an integrated circuit memory device comprising an output driver, a register and a counter is provided. The counter updates a count value in response to a signal that indicates a direction to adjust the count value.

Abstract: Error detection mechanisms for devices that have multilevel signal interfaces test multilevel signals of an interface with a binary test apparatus. The error detection mechanisms include converting between multilevel signals of the interface and binary signals of the test apparatus. The error detection mechanisms also include repeated transmission of multilevel signals stored in a memory of a device having a multilevel signal interface for detection by the test apparatus at different binary levels.

Abstract: A system transmits data on a multi-conductor signal path, which produces a current flow based on the value of the data transmitted. The system reduces changes in current flow between successive data transmissions by encoding data values represented by sets of N bits to produce corresponding sets of M symbols. Each set of M symbols represents multiple bits and each set of M symbols is selected to produce a current flow within a predetermined range of current flows. The sets of M symbols are transmitted across the multi-conductor signal path.

Abstract: A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization while maintaining the same output data latency. In one embodiment, this circuit is used on a bus-system to re-time data from receive-domain, clocks to transmit-domain clocks. In such a system the phase relationships between these two clocks is set by the device bus location and thus is not precisely known. By supporting arbitrary phase resynchronization, this disclosure allows for theoretically infinite bus-length and thus no limitation on device count, as well as arbitrary placement of devices along the bus. This ultimately allows support of multiple latency-domains for very long buses.

Abstract: An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (120), an analog voltage divider (104), an input comparator (125), a sampling latch (130), a current control counter (115), and a bitwise output driver (output driver A 107 and output driver B 111).

Abstract: A memory system and method of adjusting an output driver characteristic of a memory device that is included in the memory system. The method includes providing a command to the memory device that specifies a calibration mode and, during the calibration mode, driving a voltage level onto the first signal line using a first output driver. A first voltage level is derived from an amount of voltage swing generated by the first output driver driving the voltage level onto the first signal line. The method also includes: actively coupling a first comparator to the first signal line; when the first comparator is coupled to the first signal line, comparing the first voltage level with a reference voltage using the first comparator; and adjusting the amount of voltage swing to arrive at a calibrated voltage swing level. In addition, the method includes actively isolation the first comparator from the first signal line upon exiting the calibration mode.

Abstract: A system transmits data on a multi-conductor signal path, which produces a current flow based on the value of the data transmitted. The system reduces changes in current flow between successive data transmissions by encoding data values represented by sets of N bits to produce corresponding sets of M symbols. Each set of M symbols represents multiple bits and each set of M symbols is selected to produce a current flow within a predetermined range of current flows. The sets of M symbols are transmitted across the multi-conductor signal path.

Abstract: Error detection mechanisms for devices that have multilevel signal interfaces test multilevel signals of an interface with a binary test apparatus. The error detection mechanisms include converting between multilevel signals of the interface and binary signals of the test apparatus. The error detection mechanisms also include repeated transmission of multilevel signals stored in a memory of a device having a multilevel signal interface for detection by the test apparatus at different binary levels.

Abstract: A semiconductor controller device to control the operation of a semiconductor memory device. The controller device includes a first output driver coupled to a first output terminal, and a second output driver coupled to a second output terminal. In addition, the controller device includes a voltage divider, coupled between the first and second output terminals, to generate a control voltage based on a voltage level present on the first output terminal and a voltage level present on the second output terminal. In addition, the controller device also includes a comparator, coupled to the voltage divider, to compare the control voltage with a reference voltage, wherein an amount of voltage swing of the first output driver is adjusted based on the comparison between the control voltage and the reference voltage.

Abstract: Error detection mechanisms for signal interfaces are disclosed, including built-in self-test (BIST) mechanisms for testing multilevel signal interfaces. The error detection mechanisms may be provided in an integrated circuit (IC) chip that contains at least one of the signal interfaces or may be coupled to the interfaces on a printed circuit board (PCB). BIST mechanisms may include, for example, test signal generators and mechanisms for determining whether the test signals generated are accurately transmitted and received by the interface. The BIST mechanisms may check a single input/output interface, a group of interfaces or may operate with a master device that tests a plurality of interfaces. The error detection mechanisms may be particularly advantageous for testing memory circuits designed to communicate according to multi-PAM signals over printed circuit boards.

Abstract: A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization while maintaining the same output data latency. In one embodiment, this circuit is used on a bus-system to re-time data from receive-domain, clocks to transmit-domain clocks. In such a system the phase relationships between these two clocks is set by the device bus location and thus is not precisely known. By supporting arbitrary phase resynchronization, this disclosure allows for theoretically infinite bus-length and thus no limitation on device count, as well as arbitrary placement of devices along the bus. This ultimately allows support of multiple latency-domains for very long buses.

Abstract: An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (120), an analog voltage divider (104), an input comparator (125), a sampling latch (130), a current control counter (115), and a bitwise output driver (output driver A 107 and output driver B 111).