Abstract: An automatic test system controlled by a general purpose digital central processor is disclosed. The central processor accepts test programs in a high level compiler language such as Atlas. The Atlas program is compacted into a simplified language which is utilized to communicate with test devices via a standard IEEE 488 data bus. Each of the test devices includes a programmable interface digital processor which performs any translation that may be necessary in order to permit specific test instruments coupled to the central processor via the interface processor to perform the tests specified by the high level test programs. A switching matrix also communicates with the digital processor to connect the appropriate test device to the unit under test.

Abstract: A signal simulator for generating a simulated target signal useful in testing the receiver and data processing portions of radar systems is disclosed. Input signals to the signal simulator include a multi-pulsed synchronizing signal having substantially the same duty cycle and PRF (pulse repetition frequency) as the RF output signal of the radar transmitter normally used in conjunction with the receiver, digital signals specifying the acceleration, the initial velocity and the initial range of the target to be simulated. A target range calculator circuit utilizes the acceleration, initial velocity and initial range signals to calculate the range of a simulated target. A plurality of delay circuits are sequentially initialized by the synchronizing signal to generate a trigger signal delayed from the synchronizing signal with the delay corresponding to the range of the simulated target. The pulse width of each pulse of the synchronizing signal is measured and stored.