Patents by Inventor William F. Washburn

William F. Washburn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7145413
    Abstract: As disclosed herein, a microelectronic circuit and method are provided for improving signal integrity at a transmission line. The circuit includes a programmably adjustable impedance matching circuit which is coupled to a transmission line which includes a programmably adjustable inductive element. The programmably adjustable impedance matching circuit is desirably provided on the same chip as a receiver or transmitter to which the transmission line is coupled, or alternatively, on an element packaged together with the chip that includes the receiver or transmitter. The impedance of the programmably adjustable impedance matching circuit is adjustable in response to control input to improve signal integrity at the transmission line.
    Type: Grant
    Filed: June 10, 2003
    Date of Patent: December 5, 2006
    Assignee: International Business Machines Corporation
    Inventors: Louis L. Hsu, Joseph Natonio, Daniel W. Storaska, William F. Washburn
  • Patent number: 6975140
    Abstract: A data transmitter and transmitting method are provided in which an adaptive finite impulse response (FIR) driver has a plurality of taps to which coefficients having updateable values are applied. The FIR driver has a transfer function between an input stream of data bits and an output stream of data bits such that each data bit output from the FIR driver has an amplitude adjusted as a function of the values of a plurality of data bits of the input stream, and the values of the coefficients. The data transmitter includes a rewriteable non-volatile storage, operable to be rewritten with control information representing the values of the coefficients updated during operation of the FIR driver.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: December 13, 2005
    Assignee: International Business Machines Corporation
    Inventors: Louis L. Hsu, Brian L. Ji, William F. Washburn
  • Patent number: 6937054
    Abstract: Methods and structures are disclosed herein for programmably adjusting a peaking function of a differential signal receiver. The disclosed method includes inputting a pair of differential signals to a pair of input transistors coupled to conduct currents differentially between a pair of load impedances and a pair of tail transistors. The impedance of an adjustable shunt impedance element between the tail transistors of the receiver is varied by programming signal input, such that higher current is conducted over a peaking range of frequencies. In a disclosed structural embodiment, an integrated circuit is provided having a programmable peaking receiver. The programmable peaking receiver includes a pair of input transistors coupled to conduct differentially according to a pair of differential inputs applied to the pair of input transistors. Each of the input transistors produces an output in accordance with the differential input applied thereto.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: August 30, 2005
    Assignee: International Business Machines Corporation
    Inventors: Louis L. Hsu, Karl D. Selander, Michael A. Sorna, William F. Washburn, Huihao H. Xu, Steven J. Zier
  • Publication number: 20040251983
    Abstract: As disclosed herein, a microelectronic circuit and method are provided for improving signal integrity at a transmission line. The circuit includes a programmably adjustable impedance matching circuit which is coupled to a transmission line which includes a programmably adjustable inductive element. The programmably adjustable impedance matching circuit is desirably provided on the same chip as a receiver or transmitter to which the transmission line is coupled, or alternatively, on an element packaged together with the chip that includes the receiver or transmitter. The impedance of the programmably adjustable impedance matching circuit is adjustable in response to control input to improve signal integrity at the transmission line.
    Type: Application
    Filed: June 10, 2003
    Publication date: December 16, 2004
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Louis L. Hsu, Joseph Natonio, Daniel W. Storaska, William F. Washburn
  • Publication number: 20040239369
    Abstract: Methods and structures are disclosed herein for programmably adjusting a peaking function of a differential signal receiver. The disclosed method includes inputting a pair of differential signals to a pair of input transistors coupled to conduct currents differentially between a pair of load impedances and a pair of tail transistors. The impedance of an adjustable shunt impedance element between the tail transistors of the receiver is varied by programming signal input, such that higher current is conducted over a peaking range of frequencies. In a disclosed structural embodiment, an integrated circuit is provided having a programmable peaking receiver. The programmable peaking receiver includes a pair of input transistors coupled to conduct differentially according to a pair of differential inputs applied to the pair of input transistors. Each of the input transistors produces an output in accordance with the differential input applied thereto.
    Type: Application
    Filed: May 30, 2003
    Publication date: December 2, 2004
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Louis L. Hsu, Karl D. Selander, Michael A. Sorna, William F. Washburn, Huihao H. Xu, Steven J. Zier
  • Patent number: 5553144
    Abstract: A method and system are disclosed for selectively altering the functional characteristics of a data processing system without physical or mechanical manipulation. A data processing system is first manufactured having a predetermined set of functional characteristics. A multibit alterable code which includes a functional characteristic definition is then initially loaded into physically secure, nonvolatile memory within the data processing system, utilizing an existing bus, or a fusible link which may be opened after loading is complete. The functional characteristic definition is loaded from nonvolatile memory into a nonscannable register within a secure portion of a control logic circuit each time power is applied to the data processing system and the definition is then utilized to enable only selected functional characteristics.
    Type: Grant
    Filed: March 7, 1995
    Date of Patent: September 3, 1996
    Assignee: International Business Machines Corporation
    Inventors: Frank A. Almquist, David F. Anderson, John E. Campbell, Michael J. Chan, Stephen W. Flaherty, Steven F. Hajek, John F. Larsen, Charles H. Milligan, Cyril A. Price, Andrew M. Simon, William F. Washburn, George A. Williams, II, Roy A. Wood
  • Patent number: 4123669
    Abstract: An improved logical OR circuit is shown wherein the load resistance is divided into drain resistance and source resistance, each resistance having a lower value than could be employed with a single load resistance while at the same time keeping power dissipation to low levels. The use of relatively lower resistances permits faster voltage rise time, thereby permitting faster programmed logic array (PLA) operation. The voltage drop across the source resistance is made small when the output device is conducting by providing a substantially higher drain resistance load for the output device with respect to the drain resistance of the input devices.
    Type: Grant
    Filed: September 8, 1977
    Date of Patent: October 31, 1978
    Assignee: International Business Machines Corporation
    Inventors: William T. Devine, William F. Washburn