Abstract: A new technique for transferring data between nodes of a clustered computing system is disclosed. In one aspect, the invention includes a cluster node comprising a system bus; a memory device; and an internodal interconnect. The internodal interconnect is electrically connected to the system bus and includes a remote connection port. The internodal interconnect is capable of transferring data from the memory device and through the remote connection port. In a second aspect, a the invention includes method for internodal data transfer in a clustered computing system. Each of at least two clusters includes an internodal interconnect electrically connected to a system bus and a memory device to the system bus. The method itself comprises requesting a data transfer and then transferring the requested data. The requested data is transferred from the memory device in a first cluster node to the memory device in a second cluster node via the internodal interconnects in the first and second cluster nodes.

Abstract: A system provides a router node to bridge a LAN and a System Area Network (SAN). The router node distributes LAN traffic across the SAN using a router management agent (RMA) and a filter agent (FA); the RMA includes a session management agent (SMA), a policy management agent (PMA) and a routing agent (RA); the SMA manages connections between remote clients and SAN nodes; the PMA maintains system operation policies; the RA with the FA direct LAN packets to SAN nodes; the FA handles conversion between a SAN protocol and a LAN protocol for packets within the SAN/LAN architecture. The cluster nodes include a node management agent (NMA); the NMA includes an SMA and PMA; these two agents perform the same functions as those in the router node; and a management node sets policies on the router node and includes a monitoring agent to query router node statistics.

Abstract: A method and apparatus for reducing latency caused by cumulative point-to-point messaging associated with network performance monitoring in SAN-attached I2O architectures. In a computer system, a performance monitoring OSM associated with a first node generates status request messages to a first multicast ISM residing on a first governor IOP associated with a first node for requesting the status from all nodes. The first multicast ISM generates status request messages to all node 1 devices and node 1 IOPs and to a second multicast ISM residing on a node 2 governor IOP. The second multicast ISM generates status request messages to all node 2 devices and node 2 IOPs. One or more “unhealthy” device response messages may be sent to the performance monitoring OSM containing the TID of the “unhealthy” device to allow a subsequent point-to-point detailed status request message to be issued.

Abstract: A method for supporting multiple distributed interrupt controllers, designated as bus agents, in a symmetric multiprocessing system, which method includes the steps of assigning a unique identification number to each bus agent, receiving bus requests from the bus agents over four data lines in groups of four, and granting bus ownership to a selected one of the requesting bus agents. Similarly, a computer system that supports multiple distributed interrupt controllers, designated as bus agents, in a symmetric multiprocessing system, which computer system includes structure for assigning a unique identification number to each bus agent, four data lines for receiving bus requests from the bus agents in groups of four, and structure for granting bus ownership to a selected one of the requesting bus agents.

Abstract: Apparatus, and an associated method, converts a conventional computer peripheral device, such as an I/O (input/output) subsystem into an I.sub.2 O-aware device. An IOP mounted upon a connector card is connected to a computer bus to which the conventional computer peripheral device is connected. Once connected, the IOP, together with the conventional computer peripheral device form an I.sub.2 O-aware device.

Abstract: A method for supporting multiple distributed interrupt controllers, designated as bus agents, in a symmetric multiprocessing system, which method includes the steps of assigning a unique identification number to each bus agent, receiving bus requests from the bus agents over four data lines in groups of four, and granting bus ownership to a selected one of the requesting bus agents. Similarly, a computer system that supports multiple distributed interrupt controllers, designated as bus agents, in a symmetric multiprocessing system, which computer system includes structure for assigning a unique identification number to each bus agent, four data lines for receiving bus requests from the bus agents in groups of four, and structure for granting bus ownership to a selected one of the requesting bus agents.

Abstract: A distributed interrupt controller system for use in a multiprocessor environment, having at least two local programmable interrupt controllers (LOPICs) coupled to at least one central programmable interrupt controller (COPIC) via a dedicated bus. One of the at least one COPICs functions as a master arbiter, while the LOPICs, each of which may be integrated with its corresponding processing unit, and other non-master COPICs are treated as bus agents. Bus grant is achieved by a "round robin" arbitration protocol. For distributed delivery of interrupts, the master arbiter compares a current-task-priority-register value associated with each bus agent to determine the agent that is least busy for delivery of the interrupt thereto.

Abstract: A computer system has a central processing unit and a bus. A first bus device and a second bus device are connected to the bus. A circuit is connected to configure the second bus device to be addressable by the central processing unit via the bus only by interaction with the first bus device. The first bus device may be an I.sub.2 O processor, and the second bus device may be an I.sub.2 O subordinate bus device.

Abstract: A distributed interrupt controller system for use in a multiprocessor environment, having at least two local programmable interrupt controllers (LOPICs) coupled to at least one central programmable interrupt controller (COPIC) via a dedicated bus. One of the at least one COPICs functions as a master arbiter, while the LOPICs, each of which may be integrated with its corresponding processing unit, and other non-master COPICs are treated as bus agents. Bus grant is achieved by a "round robin" arbitration protocol. For distributed delivery of interrupts, the master arbiter compares a current-task-priority-register value associated with each bus agent to determine the agent that is least busy for delivery of the interrupt thereto.