Abstract: A brace for treating scoliosis, the brace comprising: a lower portion for disposition about the hips of a patient; an upper portion for disposition about the thorax of a patient; a first support rod adjustably extending between the lower portion and the upper portion, the first support rod being disposed at least in part along one of the front side of the patient and the back side of the patient; a second support rod adjustably extending between the lower portion and the upper portion, the second support rod being disposed at least in part along one side of the patient; wherein the lower portion, the upper portion, the first support rod and the second sup port rod are configured such that (i) the upper portion may be adjustably fixedly set substantially parallel to the lower portion, and (ii) the upper portion may be adjustably fixedly set canted at an angle to the lower portion.

Abstract: A processor isolation technique enhances debug capability in a multiprocessor circuit. A bypass register has a bit location which may indicate that a processor is to be bypassed. A code entry point is selected to permit a downstream processor to do the work of the bypassed processor. The processors may be arrayed in a pipeline.

Abstract: A processor isolation technique enhances debug capability in a highly integrated multiprocessor circuit containing a programmable arrayed processing engine for efficiently processing transient data within an intermediate network station of a computer network. The technique comprises a mechanism for programming a code entry point for each processor of a processor complex utilizing a register set that is accessible via an out-of-band bus coupled to a remote processor of the engine. The programmable entry point mechanism operates in conjunction with a bypass capability that passes transient data through a processor complex that is not functional, not running or otherwise unable to process data. Another aspect of the debug technique involves the ability to override completion control signals provided by each processor complex in order to advance a pipeline of the processing engine.