Patents by Inventor William Frederick Lawson
William Frederick Lawson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8149014Abstract: An I/O driver has v/i characteristic control for maintaining a substantially flat output impedance response using a transmission gate configuration at an I/O output pad. The configuration includes a linear resistive element electrically connected at an I/O pad for limiting a processed data I/O signal, an active impedance element for receiving and processing the data signal, which comprises data represented by a series of voltage state transitions, and pull-up and pull-down array calibration words, for generating and outputting a processed I/O output signal to the resistive element to output a substantially flat v/i response at switching of the data signal.Type: GrantFiled: October 27, 2008Date of Patent: April 3, 2012Assignee: International Business Machines CorporationInventors: David Jia Chen, William Frederick Lawson, David William Mann
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Publication number: 20090267641Abstract: An I/O driver has v/i characteristic control for maintaining a substantially flat output impedance response using a transmission gate configuration at an I/O output pad. The configuration includes a linear resistive element electrically connected at an I/O pad for limiting a processed data I/O signal, an active impedance element for receiving and processing the data signal, which comprises data represented by a series of voltage state transitions, and pull-up and pull-down array calibration words, for generating and outputting a processed I/O output signal to the resistive element to output a substantially flat v/i response at switching of the data signal.Type: ApplicationFiled: October 27, 2008Publication date: October 29, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David Jia Chen, William Frederick Lawson, David William Mann
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Publication number: 20090153216Abstract: An IO driver circuit incorporates an output stage control circuit that selectively configures an output stage for the IO driver circuit to operate as a thevenin termination whenever the IO driver circuit is receiving a signal from an input/output node to which the IO driver circuit is coupled. The output stage may include a plurality of branches, with each branch having a pull-up device and a pull-down device, and the output stage control circuit selectively activates the pull-up devices in a first subset of branches in the output stage while concurrently activating the pull-down devices in a second subset of branches, as well as while leaving the pull-up devices in the second subset of branches and the pull-down devices in the first subset of branches deactivated.Type: ApplicationFiled: December 12, 2007Publication date: June 18, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David Jia Chen, William Frederick Lawson
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Publication number: 20090085635Abstract: A design for a high speed differential voltage level shifter circuit arrangement utilizes both PFETs and NFETs controlled by inputs to determine the state of the outputs, which minimizes or eliminates contention on internal nodes when switching from one state to another. As a result, the design minimizes the adverse affects of mismatched NFET and PFET device strengths, and facilitates usage at high frequencies and for level shifting to a range of output voltage levels. The design is also adaptable for use in level shifting to higher or lower output voltages.Type: ApplicationFiled: September 28, 2007Publication date: April 2, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David Jia Chen, William Frederick Lawson
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Patent number: 7501875Abstract: A design for a high speed differential voltage level shifter circuit arrangement utilizes both PFETs and NFETs controlled by inputs to determine the state of the outputs, which minimizes or eliminates contention on internal nodes when switching from one state to another. As a result, the design minimizes the adverse affects of mismatched NFET and PFET device strengths, and facilitates usage at high frequencies and for level shifting to a range of output voltage levels. The design is also adaptable for use in level shifting to higher or lower output voltages.Type: GrantFiled: September 28, 2007Date of Patent: March 10, 2009Assignee: International Business Machines CorporationInventors: David Jia Chen, William Frederick Lawson
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Patent number: 7482838Abstract: A high-speed differential receiver is used between a high voltage domain and a low voltage domain. The high-speed differential receiver includes a common mode differential amplifier coupled to a differential level shifter. The common mode differential amplifier and differential level shifter operates at the high voltage domain. The differential level shifter receives amplified differential signals from the common mode differential amplifier and provides voltage level shifted differential signals applied to a biased differential amplifier operating at the low voltage domain.Type: GrantFiled: April 21, 2008Date of Patent: January 27, 2009Assignee: International Business Machines CorporationInventors: William Frederick Lawson, Devon Glenford Williams
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Patent number: 7443194Abstract: An I/O driver has v/i characteristic control for maintaining a substantially flat output impedance response using a transmission gate configuration at an I/O output pad. The configuration includes a linear resistive element electrically connected at an I/O pad for limiting a processed data I/O signal, an active impedance element for receiving and processing the data signal, which comprises data represented by a series of voltage state transitions, and pull-up and pull-down array calibration words, for generating and outputting a processed I/O output signal to the resistive element to output a substantially flat v/i response at switching of the data signal.Type: GrantFiled: April 24, 2008Date of Patent: October 28, 2008Assignee: International Business Machines CorporationInventors: David Jia Chen, William Frederick Lawson, David William Mann
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Publication number: 20080191745Abstract: A high-speed differential receiver is used between a high voltage domain and a low voltage domain. The high-speed differential receiver includes a common mode differential amplifier coupled to a differential level shifter. The common mode differential amplifier and differential level shifter operates at the high voltage domain. The differential level shifter receives amplified differential signals from the common mode differential amplifier and provides voltage level shifted differential signals applied to a biased differential amplifier operating at the low voltage domain.Type: ApplicationFiled: April 21, 2008Publication date: August 14, 2008Applicant: International Business Machines CorporationInventors: William Frederick Lawson, Devon Glenford Williams
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Patent number: 7385424Abstract: A high-speed differential receiver is used between a high voltage domain and a low voltage domain. The high-speed differential receiver includes a common mode differential amplifier coupled to a differential level shifter. The common mode differential amplifier and differential level shifter operates at the high voltage domain. The differential level shifter receives amplified differential signals from the common mode differential amplifier and provides voltage level shifted differential signals applied to a biased differential amplifier operating at the low voltage domain.Type: GrantFiled: June 30, 2005Date of Patent: June 10, 2008Assignee: International Business Machines CorporationInventors: William Frederick Lawson, Devon Glenford Williams
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Patent number: 7102389Abstract: A voltage translator with data buffer includes an input inverter receiving a data input signal at a first voltage level. A level shifting cross-coupled NOR circuit is coupled to the input inverter for translating the data input signal at a second voltage level. An output stage driven by the level shifting cross-coupled NOR circuit for providing a data output signal at the second voltage level. The voltage translator enables improved performance across various power, voltage and temperature (PVT) conditions and reliably reduces or minimizes shoot through current and delay.Type: GrantFiled: August 26, 2004Date of Patent: September 5, 2006Assignee: International Business Machines CorporationInventors: David Jia Chen, Michael Kevin Kerr, William Frederick Lawson
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Patent number: 6172522Abstract: A digital CMOS predriver circuit pulls an output node up and down with accurately controlled rise and fall times in the threshold region. Resistors independently set rise and fall slew rates while additional CMOS devices initially charge and discharge the output node. The additional devices turn off before the output reaches the threshold region.Type: GrantFiled: June 15, 1999Date of Patent: January 9, 2001Assignee: International Business Machines CorporationInventors: Michael Kevin Kerr, William Frederick Lawson
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Patent number: 6163169Abstract: A digital circuit pulls up an output node using an NFET device. The digital circuit is part of a CMOS predriver having balanced delays for coming out of tristate mode and for data mode operation. The predriver has size and speed capability advantages and is particularly advantageous when followed by a CMOS driver powered by a lower positive voltage supply.Type: GrantFiled: August 13, 1998Date of Patent: December 19, 2000Assignee: International Business Machines CorporationInventor: William Frederick Lawson