Abstract: Disclosed is a controller and system for state compression in memory cell. The controller comprises a processor. In one embodiment, the processor is configured to set values of D bits, based on values of M bits. M is an integer greater than 0 and D is an integer greater than 0. The controller is configured to write the values of D bits and the values of M bits into a memory cell of a non-volatile memory. In another embodiment, the controller is configured to read values of M bits and values of D bits from a memory cell of a non-volatile memory, and the controller comprises a processor configured to determine values of the M bits based on the values of the D bits.

Abstract: A controller, a method, a system, and a non-transitory machine-readable medium are provided for reducing Fail Bits Count (FBC) caused by the cross-temperature effect. In one embodiment, a controller may comprise a processor configured to obtain a record from a storage. The record comprises a representation of a programing temperature of a superblock of non-volatile memories. The non-volatile memories are on a plurality of dies. The superblock comprises blocks of the non-volatile memories and the blocks are not on the same die. The processor is further configured to determine a reference voltage based on the representation of the programing temperature and to read a page of the superblock using the reference voltage.