Abstract: A system, method and apparatus for prioritizing transactions is disclosed. I/O devices may generate transactions with a stream identifier. A transaction classifier may assign a priority to a transaction based upon a stream identifier of the transaction. An arbiter may select a transaction for processing based upon priorities assigned to the transaction.

Abstract: Apparatus and method for a first device to query a second device for the availability of a hardware feature within the second device, and for the second to receive and analyze the query to determine whether or not to respond, depending on the version of hardware feature sought, a code identifying a vendor, etc., and responding with a reply providing an indication of availability of the hardware feature and/or an address at which the hardware feature may be accessed, if the determination is made to reply.

Abstract: Write-combining in a computer system that uses a push model is set forth herein. In one embodiment, the method comprises creating one or more packets having a descriptor and the data associated with detected write transactions stored in the buffer assigned to a write-combinable range in response to a flush request to flush the buffer, and sending (pushing) these packets to the network I/O device.

Abstract: An I/O subsystem having a processor, a bridge unit, and an I/O messaging unit that couple a primary, secondary and tertiary bus in a computer system. The bridge unit is configurable to claim requests that access a messaging unit (MU) address range from the secondary bus, the MU itself being coupled to the primary bus. The MU interrupts the processor when an I/O request is posted, in response to which the processor reads from the MU pointers to an I/O messages and may then execute the I/O message. To promote the portability of software written for agents on either the primary or the secondary bus that wish to access the MU, the primary and secondary address translation units of the I/O subsystem are programmed to claim the same address translation window, where the MU address range is a portion of the primary ATU address translation window, and the secondary ATU is configured to not claim requests within the MU address range.

Abstract: Machine-readable media, methods, and apparatus are described for transferring data. In some embodiments, an operating system may allocate pages to a buffer and may build a memory descriptor list that references the pages allocated to the buffer. A direct memory access (DMA) controller may process the memory descriptor list and transfer data between a buffer defined by the memory descriptor list and another location per the memory descriptor list. The DMA controller may further support data transfers that involve buffers defined by scatter gather lists and/or chained DMA descriptors built by a device driver.

Abstract: An I/O unit for transporting a data block having a plurality of data packets across an interconnect includes an I/O controller and a memory coupled to the I/O controller for storing the data block. The I/O unit further includes a DMA object created by the controller and referring to the data block, and a transport that has a first and second VI queue pair, with each queue pair being coupled to the interconnect. The I/O unit further includes a first descriptor created by the transport and referring to a first data packet, and a second descriptor created by the transport and referring to a second data packet.

Abstract: Dynamic appending of chain descriptors is described with reference to a computer system having a host processor, a DMA unit, a host memory and an external memory wherein the DMA unit controls transference of data between the host memory and the external memory based upon data transference parameters specified in chain descriptors created by the host processor and stored as data structures within the host memory. In accordance with one method and apparatus described herein, dynamic appending of chain descriptors is achieved by employing a resume bit stored within a register of the DMA unit. The host processor, upon creating a new group of chain descriptors to be appended to a previous group, updates a link value within a last chain descriptor of the previous group to point to the first chain descriptor of the new group and also sets the resume bit within the DMA unit.