Abstract: A system and method are described for work conserving, load balancing, and scheduling by a network processor. For example, one embodiment of a system includes a plurality of processing cores, including a scheduling circuit, at least one source processing core that generates at least one task and at least one destination processing core that receives and processes the at least one task, and generates a response. The scheduling circuit of the exemplary system receives the at least one task and conducts a load balancing to select the at least one destination processing core. In an embodiment, the scheduling circuit further detects a critical sequences of tasks, schedules those tasks to be processed by a single destination processing core, and, upon completion of the critical sequence, conducts another load balancing to potentially select a different processing core to process more tasks.

Abstract: Techniques and apparatus for processor queue management are described. In one embodiment, for example, an apparatus to provide queue congestion management assistance may include at least one memory and logic for a queue manager, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine queue information for at least one queue element (QE) queue storing at least one QE, compare the queue information to at least one queue threshold value, and generate a queue notification responsive to the queue information being outside of the queue threshold value. Other embodiments are described and claimed.

Abstract: A system and method are described for work conserving, load balancing, and scheduling by a network processor. For example, one embodiment of a system includes a plurality of processing cores, including a scheduling circuit, at least one source processing core that generates at least one task and at least one destination processing core that receives and processes the at least one task, and generates a response. The scheduling circuit of the exemplary system receives the at least one task and conducts a load balancing to select the at least one destination processing core. In an embodiment, the scheduling circuit further detects a critical sequences of tasks, schedules those tasks to be processed by a single destination processing core, and, upon completion of the critical sequence, conducts another load balancing to potentially select a different processing core to process more tasks.

Abstract: A system and method are described for work conserving, load balancing, and scheduling by a network processor. For example, one embodiment of a system includes a plurality of processing cores, including a scheduling circuit, at least one source processing core that generates at least one task and at least one destination processing core that receives and processes the at least one task, and generates a response. The scheduling circuit of the exemplary system receives the at least one task and conducts a load balancing to select the at least one destination processing core. In an embodiment, the scheduling circuit further detects a critical sequences of tasks, schedules those tasks to be processed by a single destination processing core, and, upon completion of the critical sequence, conducts another load balancing to potentially select a different processing core to process more tasks.

Abstract: Apparatus and method for multi-core dynamically-balanced task processing while maintaining task order in chip multiprocessor platforms. One embodiment of an apparatus includes: a distribution circuitry to distribute, among a plurality of processing units, tasks from one or more workflows; a history list to track all tasks distributed by the distribution circuitry; an ordering queue to store one or more sub-tasks received from a first processing unit as a result of the first processing unit processing a first task; and wherein, responsive to a detection that all sub-tasks of the first task have been received and that the first task is the oldest task for a given parent workflow tracked by the history list, all sub-tasks associated with the first task are to be placed in a replay queue to be replayed in the order in which each sub-task was received.

Abstract: Apparatus and method for multi-core dynamically-balanced task processing while maintaining task order in chip multiprocessor platforms. One embodiment of an apparatus includes: a distribution circuitry to distribute, among a plurality of processing units, tasks from one or more workflows; a history list to track all tasks distributed by the distribution circuitry; an ordering queue to store one or more sub-tasks received from a first processing unit as a result of the first processing unit processing a first task; and wherein, responsive to a detection that all sub-tasks of the first task have been received and that the first task is the oldest task for a given parent workflow tracked by the history list, all sub-tasks associated with the first task are to be placed in a replay queue to be replayed in the order in which each sub-task was received.

Abstract: Techniques and apparatus for processor queue management are described. In one embodiment, for example, an apparatus to provide queue congestion management assistance may include at least one memory and logic for a queue manager, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine queue information for at least one queue element (QE) queue storing at least one QE, compare the queue information to at least one queue threshold value, and generate a queue notification responsive to the queue information being outside of the queue threshold value. Other embodiments are described and claimed.

Abstract: A system and method are described for work conserving, load balancing, and scheduling by a network processor. For example, one embodiment of a system includes a plurality of processing cores, including a scheduling circuit, at least one source processing core that generates at least one task and at least one destination processing core that receives and processes the at least one task, and generates a response. The scheduling circuit of the exemplary system receives the at least one task and conducts a load balancing to select the at least one destination processing core. In an embodiment, the scheduling circuit further detects a critical sequences of tasks, schedules those tasks to be processed by a single destination processing core, and, upon completion of the critical sequence, conducts another load balancing to potentially select a different processing core to process more tasks.

Abstract: Described embodiments provide a system having a plurality of processor cores and common memory in direct communication with the cores. A source processing core communicates with a task destination core by generating a task message for the task destination core. The task source core transmits the task message directly to a receiving processing core adjacent to the task source core. If the receiving processing core is not the task destination core, the receiving processing core passes the task message unchanged to a processing core adjacent the receiving processing core. If the receiving processing core is the task destination core, the task destination core processes the message.

Abstract: Described embodiments provide a system having a plurality of processor cores and common memory in direct communication with the cores. A source processing core communicates with a task destination core by generating a task message for the task destination core. The task source core transmits the task message directly to a receiving processing core adjacent to the task source core. If the receiving processing core is not the task destination core, the receiving processing core passes the task message unchanged to a processing core adjacent the receiving processing core. If the receiving processing core is the task destination core, the task destination core processes the message.

Abstract: The invention includes a method and apparatus for synchronizing a first processor with a second processor. The method includes storing in a register parallel bits of data from the first processor, wherein at least one bit of data is a logic ONE. An output signal is formed from the one bit of data in the register. The output signal is sent as an interrupt signal to an interrupt terminal of the second processor for synchronizing the first processor with the second processor. The method may be used with a memory mapped register or an off-core register. The first and second processors may each be a digital signal processor (DSP) or any other type of processor.

Abstract: An inter-processor data exchange system is provided in a multiple processor environment. The system includes a first message unit and a second message unit. The first message unit stores first data from a first processor and transfers the stored first data to the second message unit. The second message unit stores the first data from the first message unit and responsively provides the first data to a second processor. The second message unit also stores second data from the second processor and transfers the stored second data to the first message unit, and the first message unit stores the second data from the second message unit and responsively provides the second data to the first processor. Each message unit also provides an interrupt signal to the other processor for informing the other processor that the data is available for reading. In addition, each message unit provides a first flag signal for informing its own processor that the other processor has read the data.

Abstract: A serial interface unit having an input shift register adapted to receive a serial input data from a serial data stream, and a destination request module. The input shift register converting the serial input data into a parallel input data. The input shift register in communication with at least two processors and the destination request module. The destination request module in communication with one of the at least two processors in response to an input shift register status signal and a processor designation signal, the selected processor adapted to receive the parallel input data.

Abstract: A memory access system is provided for accessing a first data unit and a second data unit in a single memory access cycle. The memory access system provides at least a memory, an even address decoding circuit, an odd address decoder, and shift logic. The memory is interleaved by at least one address bus signal into an even memory bank and an odd memory bank. The even memory bank and the odd memory bank are each organized by a plurality of corresponding rows. Each one of the rows contains at least one storage location for a data unit, with one address mapped to one storage location. The even address decoding circuit decodes an address bus signal supplied to the input terminal and activates an output terminal coupled to enable the given row of the even memory bank. The odd address decoder decodes the address bus signal to activate an output terminal coupled to enable the row of the odd memory bank in which the first data unit resides.

Abstract: A multiple-phase clock signal generator includes a phase-locked loop (PLL) for generating an oscillating signal having a predetermined frequency, a counter driven by the oscillating signal and having a plurality of outputs, and a plurality of combinational logic gates each having a plurality of inputs and an output. Selected ones of the inputs of each combinational logic gate are coupled to selected outputs of the counter to produce, at the output of each combinational logic gate, a clock signal having a particular phase. Different combinations of the outputs of the counter can be used to generate different phases.

Abstract: A method for permanently compacting a hollow resilient structure such as a recyclable plastic container to facilitate recycling thereof. As the structure is compressed cutting blades provided on the compressing surface perforate the walls of the container thereby cutting interlocking tabs into the surface. At the same time the interlocking tabs are forced outward and through the cavity left in the walls of the container by displacement of the tabs. The tabs straddle the cavity and become locked against the walls of the container by the separating force of the resilient plastic.

Abstract: A referencing unit which creates addresses for main memory. Specifically, this reference unit is pipelined in the manner in which it receives the operators to be executed. Concurrency is achieved by allowing any number of read-type operations to be started before operators that are waiting for a store operation to finish even though these latter operators may appear earlier in the code stream. There are two inputs into the reference unit. Each is provided with a queue, one for receiving operators and address couples and another for receiving the output from the top-of-the-stack mechanism residing in the processor. The former is called an address coupled queue and the latter is called a top-of-stack queue. Since the address couple queue operators require no stack inputs, they enter the reference pipeline, two pipeline levels below where the top-of-stack operators enter the pipeline.