Patents by Inventor William G. Kulpa
William G. Kulpa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7921188Abstract: A computer system is described having a plurality of resources which includes a plurality of processors, a distributed point-to-point transmission infrastructure for interconnecting the plurality of processors, and a partitioning processor for configuring the plurality of resources into at least one partition. Each partition comprises a subset of the plurality of resources. The partitioning processor is operable to configure the resources by enabling at least one link between at least one of the plurality of processors and at least one other one of the plurality of processors according to a previously specified partitioning schema. The link(s) so enabled corresponds to a portion of the point-to-point transmission infrastructure.Type: GrantFiled: August 16, 2001Date of Patent: April 5, 2011Assignee: Newisys, Inc.Inventors: Richard R. Oehler, William G. Kulpa
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Patent number: 7577755Abstract: Methods and apparatus are provided for improving the distribution of system management signals within a computer system complex. Mechanisms are provided for transmission both within a box and between computer system boxes. Local routing tables and general routing tables allow the distribution of system management signals precisely to resources associated with particular partitions. Signals are sequenced to put resources associated with one or more boxes in the appropriate states. The distribution of signals between boxes in the computer system complex can be accomplished without the use of a dedicated wire.Type: GrantFiled: November 19, 2002Date of Patent: August 18, 2009Assignee: Newisys, Inc.Inventors: Carl Zeitler, David Brian Glasco, Les Record, Richard R. Oehler, William G. Kulpa, Guru Prasadh, Rajesh Kota
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Patent number: 7418517Abstract: Methods and apparatus are provided for improving the distribution of system management signals within a computer system complex. Mechanisms are provided for transmission both within a box and between computer system boxes. Local routing tables and general routing tables allow the distribution of system management signals precisely to resources associated with particular partitions. Signals are sequenced to put resources associated with one or more boxes in the appropriate states. The distribution of signals between boxes in the computer system complex can be accomplished with the use of a dedicated wire.Type: GrantFiled: January 30, 2003Date of Patent: August 26, 2008Assignee: Newisys, Inc.Inventors: Carl Zeitler, David Brian Glasco, Les Record, Richard R. Oehler, William G. Kulpa, Guru Prasadh, Rajesh Kota
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Patent number: 7019983Abstract: An electronic assembly is described which includes a printed circuit board, and a processor and a memory mounted on the printed circuit board. A routing channel is provided in the printed circuit board comprising a plurality of conductors interconnecting the processor and the memory. A regulator assembly includes a regulator for providing power to the processor, a first connector mounted on the printed circuit board adjacent a first edge of the routing channel, and a second connector mounted on the printed circuit board adjacent a second edge of the routing channel opposite the first edge. The first and second connectors are coupled to the regulator and facilitate distribution of the power to the processor. The regulator and the first and second connectors form a bridge across the routing channel.Type: GrantFiled: June 23, 2003Date of Patent: March 28, 2006Assignee: Newisys, Inc.Inventors: Leslie J. Record, William G. Kulpa, Robert Gontarek
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Publication number: 20040257781Abstract: An electronic assembly is described which includes a printed circuit board, and a processor and a memory mounted on the printed circuit board. A routing channel is provided in the printed circuit board comprising a plurality of conductors interconnecting the processor and the memory. A regulator assembly includes a regulator for providing power to the processor, a first connector mounted on the printed circuit board adjacent a first edge of the routing channel, and a second connector mounted on the printed circuit board adjacent a second edge of the routing channel opposite the first edge. The first and second connectors are coupled to the regulator and facilitate distribution of the power to the processor. The regulator and the first and second connectors form a bridge across the routing channel.Type: ApplicationFiled: June 23, 2003Publication date: December 23, 2004Applicant: Newisys, Inc.Inventors: Leslie J. Record, William G. Kulpa, Robert Gontarek
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Publication number: 20040153507Abstract: Methods and apparatus are provided for improving the distribution of system management signals within a computer system complex. Mechanisms are provided for transmission both within a box and between computer system boxes. Local routing tables and general routing tables allow the distribution of system management signals precisely to resources associated with particular partitions. Signals are sequenced to put resources associated with one or more boxes in the appropriate states. The distribution of signals between boxes in the computer system complex can be accomplished with the use of a dedicated wire.Type: ApplicationFiled: January 30, 2003Publication date: August 5, 2004Applicant: Newisys, Inc. A Delaware corporationInventors: Carl Zeitler, David Brian Glasco, Les Record, Richard R. Oehler, William G. Kulpa, Guru Prasadh, Rajesh Kota
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Publication number: 20040098475Abstract: Methods and apparatus are provided for improving the distribution of system management signals within a computer system complex. Mechanisms are provided for transmission both within a box and between computer system boxes. Local routing tables and general routing tables allow the distribution of system management signals precisely to resources associated with particular partitions. Signals are sequenced to put resources associated with one or more boxes in the appropriate states. The distribution of signals between boxes in the computer system complex can be accomplished without the use of a dedicated wire.Type: ApplicationFiled: November 19, 2002Publication date: May 20, 2004Applicant: Newisys, Inc., A Delaware CorporationInventors: Carl Zeitler, David Brian Glasco, Les Record, Richard R. Oehler, William G. Kulpa, Guru Prasadh, Rajesh Kota
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Publication number: 20030037224Abstract: A computer system is described having a plurality of resources which includes a plurality of processors, a distributed point-to-point transmission infrastructure for interconnecting the plurality of processors, and a partitioning processor for configuring the plurality of resources into at least one partition. Each partition comprises a subset of the plurality of resources. The partitioning processor is operable to configure the resources by enabling at least one link between at least one of the plurality of processors and at least one other one of the plurality of processors according to a previously specified partitioning schema. The link(s) so enabled corresponds to a portion of the point-to-point transmission infrastructure.Type: ApplicationFiled: August 16, 2001Publication date: February 20, 2003Applicant: Newisys, Inc.Inventors: Richard R. Oehler, William G. Kulpa
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Patent number: 5155807Abstract: A system for transferring data between a pair of data processing units having system buses includes a plurality of memories in each of the data processing units; each memory having a random access portion and an associated sequential access portion; means for transferring data between each of the random access portions of each of the memories and its associated sequential access portion; and means connecting the sequential access portions of each of the memories in one of the data processing units to the sequential access portions of the other of said data processing units to permit data flow therebetween; the data flow between the sequential access portions of said memories occurring asynchronously of the remainder of the system so that the data processing units can utilize their system buses during such data flow.Type: GrantFiled: September 14, 1990Date of Patent: October 13, 1992Assignee: International Business Machines CorporationInventors: Ballard J. Blevins, William G. Kulpa, Joseph R. Mathis
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Patent number: 4695948Abstract: An improvement in a bus converter that provides a bus to bus address translation function permitting access from an I/O device connected on the I/O bus to a system bus and system memory, where the bus converter includes a circuit connected to the I/O bus to partition I/O addresses received from the I/O bus into a lower order field and a high order field and connected to a circuit to receive DMA ID's from the I/O bus to combine this DMA ID with the high order field to form a first combined address. The first combined address is input to a memory which provides corresponding control field and prefix field data. An address formatter is further included that is connected to receive the control field and prefix field data from the memory and further connected to receive the low order address field. The address formatter forms a second combined address from the prefix field, control field and lower order address field. This second combined address is then provided to a system bus to permit access to the system bus.Type: GrantFiled: February 28, 1985Date of Patent: September 22, 1987Assignee: International Business Machines CorporationInventors: Ballard J. Blevins, William G. Kulpa, Joseph R. Mathis, John W. McCullough