Abstract: A two-stage RF amplifier comprising first and second transistors arranged in cascode. An input stage includes a common source transistor having a gate terminal responsive to an input signal and an output stage includes a common gate transistor having a source terminal operatively connected to the drain terminal of the common source transistor. A shunt feedback network is arranged between a drain terminal of the common gate transistor and the gate terminal of the common source transistor. A source feedback network is arranged between the source terminal of the common source transistor and a reference potential. A common gate feedback network is arranged between the drain terminal of the common gate transistor and a gate terminal of the common gate transistor. And a termination feedback network is arranged in series between the reference potential and the gate terminal of the common gate transistor.

Abstract: A phase shifter comprises a differential quadrature all-pass filter (QAF) including a balanced input port and two balanced output ports. A quadrature phase shift is manifested between the balanced output ports. The phase shifter also comprises a resistance-capacitance polyphase filter (PPF) section defining two balanced input ports and two balanced output ports. The balanced input ports of the PPF are coupled to the balanced output ports of the QAF. The combination exhibits broad bandwidth and relatively low ohmic loss.

Abstract: A representative integrated circuit comprises a clock signal generator that generates a clock signal, a code pattern generator that generates digital pattern data based on the clock signal, and multiple traversal local oscillator synthesizers that are coupled in a cascaded configuration. Each traversal local oscillator synthesizer includes a transversal digital-to-analog conversion (T-DAC) unit that includes a plurality of registers and a unary modulator (Umod) array. The T-DAC provides frequency selection ranges covering wide operational bands based on the digital pattern data and the clock signal.

Abstract: A level shifting circuit includes a string of diodes and an active load across which the control voltage is applied. A resistor is coupled across the lowermost diode to develop a switch control voltage. At low control voltage, the diode string allows no current to be developed across the resistor. At higher control voltage, the diodes conduct and the active load takes up the difference between the control voltage and the diode string voltage. A switch responds to the resistor voltage, for switching a load On and OFF. A second active load takes up excess load supply voltage.

Abstract: A system includes a source of electromagnetic energy or power and an amplitude-sensitive circuit. An amplitude-limiting transmission line couples the source to the circuit. The transmission line includes a semiconductor in the field of the transmission line and a light source for illuminating the semiconductor with light responsive to the amplitude from the source. Application of energy or power to the light source illuminates the semiconductor, which produces a plasma. The plasma tends to attenuate the energy or power reaching the circuit.

Abstract: A representative integrated circuit comprises a clock signal generator that generates a clock signal, a code pattern generator that generates digital pattern data based on the clock signal, and multiple traversal local oscillator synthesizers that are coupled in a cascaded configuration. Each traversal local oscillator synthesizer includes a transversal digital-to-analog conversion (T-DAC) unit that includes a plurality of registers and a unary modulator (Umod) array. The T-DAC provides frequency selection ranges covering wide operational bands based on the digital pattern data and the clock signal.