Abstract: A frequency synthesizer with at least two main Phase Locked Loops (PLLs) and a signal combiner, where each PLL's input is driven by a reference source of frequency F.sub.refj, and each PLL has programmable dividers in both its input path (M and P) and its feedback path (N and Q). The synthesizer utilizes a method to produce an output frequency F.sub.out that is a close approximation to a requested frequency F.sub.req. The method includes making a series of rational fraction approximations .sup.X i/Y.sub.i to the ratio .sup.F req/F.sub.refj, factoring the resulting Y.sub.i 's into several factors M.sub.i and P.sub.i, picking a pair X.sub.k, Y.sub.k that is a good approximation, but where neither M.sub.k nor P.sub.k is too large for the dividers, and then using diophantine calculation methods and a further equation relating to the way the PLL's signals are combined, to calculate N.sub.k and Q.sub.k. The integers M.sub.k, N.sub.k, P.sub.k, and Q.sub.k are then used to program the four dividers.

Abstract: A frequency synthesizer with at least one main Phase Locked Loop (PLL), where the PLL has programmable dividers in both its input path (M) and its feedback path (N), and where the main PLL is driven by a reference source of frequency F.sub.ref and has output F.sub.out =.sup.N /.sub.M *F.sub.ref, and each of the programmable counters is controlled by a calculation and control device. The synthesizer uses a method to produce an output frequency F.sub.out that is a close approximation to a requested frequency F.sub.req, including calculating several integer approximations .sup.N i/M.sub.i to the ratio .sup.F req/F.sub.ref, and picking the best approximation where the values of N.sub.i and M.sub.i are both still small enough to be used to program the two programmable counters. In another form of the invention, there is an adjustable reference source which can provide a plurality of reference frequencies F.sub.refj under control of the calculation and control device. Here, a value of F.sub.

Abstract: A frequency synthesizer comprising at least two main PLL's, where each PLL has programmable dividers in both its input path (M and P) and its feedback path (N and Q), and where the first PLL is driven by a reference source of frequency F.sub.ref and has output Fl=(.sup.N /.sub.M) *F.sub.ref, and where this output serves as the input to the second main PLL, whose output in turn is F.sub.out =(.sup.Q /.sub.P) *Fl=(.sup.Q /.sub.P)*(.sup.N /.sub.M)*F.sub.ref, and each of the programmable counters is controlled by a calculation and control means, said synthesizer utilizing a method to produce an output frequency F.sub.out that is a close approximation to a requested frequency F.sub.req. The method includes doing several approximations to the ratio .sup.F req/F.sub.ref, and picking the best, calculating the four integers, generating several signals, and dividing them by said integers, locking said loops, and thereby producing F.sub.out. In one form of the invention, an approximation .sup.X 1/Y.sub.

Abstract: An electronic circuit for selectively generating two output pulses that differ in duration by a predetermined amount has a clock terminal for receiving clock transitions at precisely determined intervals and comprises first and second sequential logic devices, a combinational logic device and a network that couples the clock terminal of the circuit to the sequential logic devices and also couples the second sequential logic device to the combinational logic device. The first and second sequential logic devices each have a data input terminal, a clock input terminal and an output terminal, and each has a first state in which the output terminal is at one of two binary logic levels and a second state in which the output terminal is at the other of the two binary logic levels.

Abstract: An apparatus for calibrating a timer of the type having a first and a second input channel in which an initial signal arriving over one input channel initiates a timing cycle, while a subsequent signal arriving over the other input channel terminates the timing cycle, the initial and subsequent signals being transported to remote ends of the first and second input channels from remote sources by means of first and second signal conductors. The apparatus comprises a commoning conductor, a test signal source, and first and second signal routing networks, the first signal routing network being capable of selectively coupling the first signal cable, the test signal source, one end of the commoning cable, and the first timer input channel, while the second signal routing network is capable of selectively coupling the second signal cable, the test signal source, or another end of the commoning cable and the second timer input channel.

Abstract: A method and apparatus for automatically detecting peak values of an applied unknown electrical signal employ a binary search technique in which a digital signal is converted to analog reference voltage levels one bit at a time from the most significant bit to the least significant bit to be compared with the unknown signal until finally a digital signal is produced which corresponds to a peak value. By selecting and controlling the comparator slope, both positive and negative peaks may be detected. The search for positive and negative peaks of signals occurring in one or more signal channels may be interleaved to decrease total detection time. From the detected values, a triggering voltage level may be arithmetically computed.

Abstract: A gating circuit for a universal counter comprises a pair of flip-flops and a pair of logic gates arranged to provide any of a plurality of counting or timing measurements. A gate control circuit includes a control logic unit to provide routing and synchronization of digital signals from several inputs, including an internal source as well as a pair of external sources, into one or both of a pair of count chains.

Abstract: A circuit including a peak detector detects the distortion of the leading corner of a square-wave reference signal in the over-compensated condition of an attenuator probe and turns on an indicator light. The light turns off as the probe is adjusted to the properly compensated condition because the distortion is no longer detected.

Abstract: A device for monitoring a variable voltage supply level is disclosed. The monitoring device functions to supply a signal which may be used to shut-down that equipment being supplied and/or drive an indicating device when the voltage level is below a trip voltage and, when the voltage level exceeds the trip voltage to provide a signal which may be used to reconnect the equipment circuit. The monitoring device includes a pair of low power generators each of which produce a digital signal. The digital signal of one generator varies more than the digital signal of the other generator with changes in applied voltage. The two digital signals are compared by a low power circuit and voltage level information is determined.