Abstract: A method for implementing shared metal connectivity between 3D stacked circuit dies can include providing a first circuit die having a first metal stack. The method can additionally include providing a second circuit die having a second metal stack, wherein at least one metal layer of the second metal stack is utilized by both the first circuit die and the second circuit die. The method can also include connecting the second metal stack to the first metal stack of the first circuit die. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A method for die pair partitioning can include providing a circuit die that has a metal stack and that includes a majority of logic transistors of an integrated circuit. The method can also include providing one or more additional circuit die that have one or more additional metal stacks of which at least one is connected to the metal stack of the circuit die and a majority of static random access memory and analog devices of the integrated circuit. The method can further include connecting at least one of the one or more additional metal stacks to the metal stack of the circuit die. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: An integrated circuit with a semiconductor substrate is provided. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. A silicide layer is on the semiconductor substrate adjacent the gate and the gate dielectric. The silicide layer incorporates a substantially uniformly distributed and concentrated dopant therein. A shallow source/drain junction is beneath the salicide layer. An interlayer dielectric is above the semiconductor substrate, and contacts are in the interlayer dielectric to the salicide layer.

Abstract: A gate structure is formed overlying a substrate. A source/drain region of the substrate is exposed to a soluction comprising ammonium hydroxide, hydrogen peroxide, and deionized water to etch an upper-most semiconductor porton of the source/drain region.

Abstract: A method for forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate adjacent the gate. A facet is formed in at least one of the source/drain junctions of the integrated circuit.

Abstract: A structure, for testing relative to an MOS transistor, closely resembles the MOS transistor of interest. For example, certain dimensions and a number of dopant concentrations typically are substantially the same in the test structure as found in corresponding elements of the MOS transistor of interest. However, the regions of the test structure corresponding to the source and drain of the transistor have no halos or extensions that might cause gate overlap; and in the test structure, these regions are of a semiconductor type opposite the type found in the source and drain of the transistor. The test structure enables accurate measurement of the gate-body current, for modeling floating body effects and/or for direct electrical measurement of gate length.

Abstract: A structure for testing relative to an MOS transistor, can be easily constructed as part of the CMOS process flow. A doped device well is formed, for example, in a silicon-on-insulator structure. The concentration level in the well corresponds to that for a well of the transistor. Gate insulator and polysilicon layers are formed, and the polysilicon is implanted with dopant, to a concentration level expected in the transistor gate. After gate patterning, the methodology involves forming sidewall spacers and implanting dopant into the active device well, to form regions in the test structure corresponding to the transistor source and drain. Although the concentrations mimic those in the transistor source and drain, these test structure regions are doped with opposite type dopant material. The test structure enables accurate measurement of the gate-body current, for modeling floating body effects and/or for measurement of gate length.

Abstract: A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. A super-saturated doped source silicide metallic layer is formed on the semiconductor substrate adjacent the gate and the gate dielectric. The silicide metallic layer incorporates a substantially uniformly distributed dopant therein in a substantially uniform super-saturated concentration. The silicide metallic layer is reacted with the semiconductor substrate therebeneath to form a salicide layer and outdiffuse the dopant from the salicide layer into the semiconductor substrate therebeneath. The outdiffused dopant in the semiconductor substrate is then activated to form a shallow source/drain junction beneath the salicide layer. An interlayer dielectric is then deposited above the semiconductor substrate, and contacts are formed in the interlayer dielectric to the salicide layer.

Abstract: A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. A raised source/drain layer is formed on the semiconductor substrate adjacent the gate and the gate dielectric. An amorphized shallow source/drain extension implanted region is formed in the raised source/drain layer and the semiconductor substrate therebeneath. The amorphized region is then recrystallized to form a shallow source/drain extension having residual recrystallization damage elevated into the raised source/drain layer.

Abstract: A method for manufacturing an integrated circuit on a semiconductor wafer is provided. The semiconductor wafer has complete die and partial die areas thereon. Functional circuit patterns are formed in a plurality of the complete die areas. The thermal absorption properties of the semiconductor wafer are tuned by forming differing patterns in a plurality of the partial die areas.

Abstract: A semiconductor device formed on a semiconductor substrate having an active region and a method of making the same is disclosed. The semiconductor device includes a dielectric layer interposed between a gate electrode and the semiconductor substrate. Further, the semiconductor device includes graded dielectric constant spacers formed on sidewalls of the dielectric layer, sidewalls of the gate electrode and portions of an upper surface of the semiconductor substrate. The dielectric constant of the graded dielectric constant spacers decreases in a direction away from the sidewalls of the dielectric layer.

Abstract: A device and method for making a semiconductor-on-insulator (SOI) structure having a leaky, thermally conductive material (LTCIM) layer disposed between a semiconductor substrate and a semiconductor layer.

Abstract: Methods are described for fabricating semiconductor devices, in which a tensile film is formed over PMOS transistors to cause a compressive stress therein and a compressive film is formed over NMOS transistors to achieve a tensile stress therein, by which improved carrier mobility is facilitated in both PMOS and NMOS devices.

Abstract: A semiconductor-on-insulator (SOI) device formed on an SOI structure with a buried oxide (BOX) layer disposed therein and an active region disposed on the BOX layer having active regions defined by isolation trenches and the BOX layer. The SOI device includes a gate formed over one of the active regions. The gate defines a channel interposed between a source and a drain formed within one of the active regions. The SOI device includes a leakage enhanced region within the BOX layer defined by the gate.

Abstract: A device and method for making a semiconductor-on-insulator (SOI) structure having a leaky, thermally conductive material (LTCIM) layer disposed between a semiconductor substrate and a semiconductor layer.

Abstract: A device and method for making a semiconductor-on-insulator (SOI) structure having an insulator layer disposed between a semiconductor substrate and a semiconductor layer. An interface between the insulator layer and the semiconductor layer bleeds off extra carriers. Active regions are defined in the semiconductor layer by isolation trenches and the insulator layer.

Abstract: The present invention provides a method and system for providing electrical insulation for local interconnect in a logic circuit. A system and method according to the present invention for providing electrical installation for local interconnects during manufacturing of a logic circuit comprising the steps of providing a first layer of material over a semiconductor wafer and providing a second layer of material over the first layer. Additionally, a photoresist material is provided over a portion of the logic circuit to be electrically insulated. Portions of the first and second layers which are unprotected by the photoresist material are then etched. At least a third layer is then provided over the first and second layers, and the third layer is etched such that the first layer as an electrical insulation over the portion of the logic circuit.

Abstract: The present invention provides a method and system for providing electrical insulation for local interconnect in a logic circuit. A system and method according to the present invention for providing electrical installation for local interconnects during manufacturing of a logic circuit comprising the steps of providing a first layer of material over a semiconductor wafer and providing a second layer of material over the first layer. Additionally, a photoresist material is provided over a portion of the logic circuit to be electrically insulated. Portions of the first and second layers which are unprotected by the photoresist material are then etched. At least a third layer is then provided over the first and second layers, and the third layer is etched such that the first layer as an electrical insulation over the portion of the logic circuit.

Abstract: A plasma charging damage protection structure (40, 104) includes a first conduction path (90) for conducting positive plasma charging away from a device needing protection (44) and a second conduction path (94) for conducting negative plasma charging away from the device needing protection (44). In addition, a method (200) of preventing plasma induced charging damage includes the forming of plasma charging during semiconductor processing (202). The method also includes conducting the plasma charging through a first conduction path if the plasma charging is positive (210) and conducting the plasma charging through a second conduction path if the plasma charging is negative (214).

Abstract: The present invention provides a method and system for providing electrical insulation for local interconnect in a logic circuit. A system and method according to the present invention for providing electrical installation for local interconnects during manufacturing of a logic circuit comprising the steps of providing a first layer of material over a semiconductor wafer and providing a second layer of material over the first layer. Additionally, a photoresist material is provided over a portion of the logic circuit to be electrically insulated. Portions of the first and second layers which are unprotected by the photoresist material are then etched. At least a third layer is then provided over the first and second layers, and the third layer is etched such that the first layer as an electrical insulation over the portion of the logic circuit.