Abstract: Aspects disclosed in the detailed description include integrated circuit (IC) design methods using engineering change order (ECO) cell architectures. In particular, exemplary aspects provide a fill algorithm that is both single- and multi-row aware, considers a poly-pitch count, and utilizes metallization of the “empty space” relative to a suite of available fill cells. The algorithm is also aware of timing critical logic elements and may place ECO fill cells in near proximity to such timing sensitive circuits or other margin critical circuits to allow for decoupling or, if there is a logic error, an ECO cell is placed such that the ECO cell is well positioned to be repurposed as a delay circuit or other function to aid in margin control. For maximum flexibility, the algorithm may also address both pre- and post-route applications.

Abstract: Disclosed systems and methods pertain to finfet based integrated circuits designed with logic cell architectures which support multiple diffusion regions for n-type and p-type diffusions. Different diffusion regions of each logic cell can have different widths or fin counts. Abutting two logic cells is enabled based on like fin counts for corresponding p-diffusion regions and n-diffusion regions of the two logic cells. Diffusion fills are used at common edges between the two logic cells for extending lengths of diffusion, based on the like fin counts. The logic cell architectures support via redundancy and the ability to selectively control threshold voltages of different logic cells with implant tailoring. Half-row height cells can be interleaved with standard full-row height cells.

Abstract: Aspects disclosed in the detailed description include integrated circuit (IC) design methods using engineering change order (ECO) cell architectures. In particular, exemplary aspects provide a fill algorithm that is both single- and multi-row aware, considers a poly-pitch count, and utilizes metallization of the “empty space” relative to a suite of available fill cells. The algorithm is also aware of timing critical logic elements and may place ECO fill cells in near proximity to such timing sensitive circuits or other margin critical circuits to allow for decoupling or, if there is a logic error, an ECO cell is placed such that the ECO cell is well positioned to be repurposed as a delay circuit or other function to aid in margin control. For maximum flexibility, the algorithm may also address both pre- and post-route applications.

Abstract: Engineering change order (ECO) cell architecture and implementation is disclosed. In particular, exemplary aspects disclosed herein provide a generic cell structure that may be readily modified to effect an ECO without requiring extensive mask changes beyond one or two levels including the level in which the cell is located. Further, this generic cell structure can be “parked” fairly deep in the manufacturing process, such as in the middle-end-of-line (MEOL), so that fewer changes to other masks are needed in the event of a change. The generic cell may further act as a filler cell for pattern density. Inclusion of such a generic cell in a circuit design can help alleviate the need for extensive mask redesign and accompanying delays in the production of finished silicon.

Abstract: Disclosed systems and methods pertain to finfet based integrated circuits designed with logic cell architectures which support multiple diffusion regions for n-type and p-type diffusions. Different diffusion regions of each logic cell can have different widths or fin counts. Abutting two logic cells is enabled based on like fin counts for corresponding p-diffusion regions and n-diffusion regions of the two logic cells. Diffusion fills are used at common edges between the two logic cells for extending lengths of diffusion, based on the like fin counts. The logic cell architectures support via redundancy and the ability to selectively control threshold voltages of different logic cells with implant tailoring. Half-row height cells can be interleaved with standard full-row height cells.

Abstract: Complementary metal oxide semiconductor (MOS) (CMOS) standard cell circuits employing metal lines in a first metal layer used for routing, and related methods are disclosed. In one aspect, a CMOS standard cell circuit includes first supply rail, second supply rail, and metal lines disposed in the first metal layer. One or more of the metal lines are dynamically cut corresponding to a first cell boundary and a second cell boundary of the CMOS standard cell such that the metal lines have cut edges corresponding to the first and second cell boundaries. Metal lines not cut corresponding to the first and second cell boundaries can be used to interconnect nodes of the CMOS standard cell circuit. Dynamically cutting the metal lines allows the first metal layer to be used for routing, reducing routing in other metal layers such that fewer vias and metal lines are disposed above the first metal layer.

Abstract: The invention provides a method for preparing a hydrogel from a hydrophilic polymer having one or more functional groups which are capable of co-reacting in a condensation reaction which method comprises the steps of: (i) preparing a solution of the polymer; (ii) heating the solution to a temperature sufficient for the condensation reaction to take place for a period of time sufficient for the hydrogel to cross-link wherein where the hydrophilic polymer comprises a first and a second hydrophilic polymer, step (i) comprises a step of mixing the hydrophilic polymers to prepare a homogeneous intimate mixture of the polymers; and wherein the heating step (ii) is carried out at a pressure greater than atmospheric pressure. The method of the invention is advantageous because it is relatively low cost, it is a safer procedure with less health & safety concerns, it is carried out in a liquid state and is not limited by film thickness.

Abstract: A film-forming binder polymer for a coating composition such as a paint, varnish or woodstain where the polymer is modified by the presence of bonded moieties derived from plant gum, particularly plant fibre gum obtainable from plant fibre, especially corn fibre gum and more particularly moieties derived from proteo-xylans and/or furanose. The modified binder polymer minimises the need to use coalescing solvents without producing poor dried paint coatings which fail the scrub resistance tests also improves the opacity of the dried coating composition.

Abstract: A film-forming binder polymer for a coating composition such as a paint, varnish or woodstain where the polymer is modified by the presence of bonded moieties derived from plant gum, particularly plant fibre gum obtainable from plant fibre, especially corn fibre gum and more particularly moieties derived from proteo-xylans and/or furanose. The modified binder polymer minimises the need to use coalescing solvents without producing poor dried paint coatings which fail the scrub resistance tests also improves the opacity of the dried coating composition.

Abstract: A fluid leak alert system comprises a flow sensor and a timer apparatus. The flow sensor is configured for sensing presence of fluid flow through a fluid flow line. The timer apparatus is connected to the flow sensor. The timer apparatus compares a prescribed maximum flow interval duration to a length of time over which the presence of fluid flow through the fluid flow line is sensed for determining if the length of time that fluid flow is present is greater than the prescribed maximum flow interval duration. The timer apparatus outputs an alert signal when the length of time is greater than the prescribed maximum flow interval duration. The timer apparatus includes a flow interval duration adjuster for enabling the prescribed maximum flow interval duration to be selectively set to any one of a plurality of different prescribed maximum flow interval durations.

Abstract: A multimode, uniform-latency clock generation circuit (CGC) is described herein. In one example, the multimode, uniform-latency CGC generates a pulse clock signal via a clock generation path responsive to a clock chopping signal being active and generates a phase clock signal via the same clock generation path responsive to the clock chopping signal being inactive. The clock chopping signal is activated responsive to a mode control input signal being in a first state and deactivated responsive to either the mode control input signal being in a second state or a plurality of clock enable signals being inactive. In one or more embodiments, a multimode, uniform-latency CGC is included in a microprocessor for providing pulse clock signals to inter-stage pulsed sequential storage elements when operating in a timing sensitive mode and for providing phase clock signals to the inter-stage pulsed sequential storage elements when operating in a timing insensitive mode.

Abstract: A multi-enabled clock gating circuit reduces clock enable setup time. In one example, the multi-enabled clock gating circuit comprises an OAI logic gate and a clock enable control circuit. The OAI logic gate is configured to generate a gated clock signal by inverting an input clock signal responsive to one of a timing-sensitive clock enable signal and a timing-insensitive clock enable signal being active. The clock enable control circuit is configured to prevent the OAI logic gate from receiving the timing-insensitive clock enable signal responsive to the timing-sensitive clock enable signal being active. In one or more embodiments, a multi-enabled clock gating circuit having reduced clock enable setup time may be included in an integrated circuit for implementing clock gating during different operating modes of the integrated circuit.