Abstract: In one embodiment, an interconnect object in a layout of an integrated circuit design to be created with a photolithographic process is determined. The interconnect object includes a width and a length in the layout. A contour generation of the interconnect object in a drawn design is determined based on processing variation factors for the photolithographic process, which produces a generated contour object. A plurality of segments in the generated contour object may be determined based on processing variations. Segments are then broken up based on the processing variations that result. An adjusted width and adjusted length for each of the plurality of segments of the generated contour object are then determined. Resistances and capacitances may be extracted using the adjusted widths and adjusted lengths. Then, the output of the LVS tool may be sent to a SPICE simulation to verify the electrical behavior of the interconnect.

Abstract: In one embodiment, a method for determining a contour simplification of an object for a simulation is provided. An object in a layout of a transistor design to be created with the photolithographic process is determined. The object includes a width and a length in the layout. A contour simulation is performed to determine a generated contour object. The contour simulation simulates parametric variation factors that may occur in the photolithographic process. An adjusted width and adjusted length of the object is then determined based on the generated contour object. The adjusted width and the adjusted length are usable to determine a parametric model for simulation of the object. For example, a layout versus schematic (LVS) tool may back-annotate the layout. Then, a SPICE simulation may use the output of the LVS tool to verify the electrical behavior of the transistor using the adjusted width and adjusted length.

Abstract: A design methodology reduces electromigration in integrated circuit joints such as flip-chip bumps by seeking to produce a more uniform current distribution at the interface between the integrated circuit pad and the joint while maintaining an interface form that coincides with standard integrated circuit designs is presented. The design methodology addresses the current distribution at the pad by introducing an intermediate trace routing design between the current delivering trace and the pad that distributes the inflow of current from the trace to multiple points of entry on the pad. The intermediate trace routing design includes an outer trace channel connected to the current delivering trace. A plurality of conductive trace leads connect the outer trace channel to the pad. Preferably, each of the plurality of conductive trace leads is characterized by a respective trace impedance so as to distribute equal current flow through each of the leads to the pad.

Abstract: A novel pad structure for an integrated circuit component that utilizes a bump interconnect for connection to other integrated circuit components that produces a relatively uniform current distribution within the bump of the bump interconnect is presented. The pad structure includes an inner pad implemented on an inner conductive layer of the integrated circuit component, an outer pad implemented on an outer conductive layer of the integrated circuit component, and a plurality of vias connecting the inner pad and outer pad. The outer pad is sealed preferably around its edges with a passivation layer, which includes an opening exposing a portion of the outer pad. The vias connecting the inner pad and outer pad are preferably implemented to lie in a via region within the footprint of the pad opening.