Abstract: A field programmable gate array (FPGA) including both routing and logic blocks (RLBs) and routing and arbiter blocks (RABs) is disclosed. The RABs are periodically placed throughout the FPGA and operate either to arbitrate the arrival of simultaneous signals or to synchronize simultaneous signals. In addition, each of the RLBs are capable of operating in accordance with two clock signals and an asynchronous initialization. The combination of the RLBs and RABs allow the FPGA to operate synchronously and asynchronously.

Abstract: A field programmable gate array (FPGA) comprising routing and logic blocks (RLBs) and segmented routing channels is disclosed. Each RLB is configurable to perform both logic functions and routing functions. A plurality of forwardly propagating RLBs (FPRLBs) and a plurality of backwardly propagating RLBs (BPRLBs) intermesh with one another to form a two-dimensional checkerboard array. Each column of the RLB array comprises a plurality of FPRLBs and BPRLBs in alternating sequence. Similarly, each row of the RLB array comprises a plurality of FPRLBs and BPRLBs in alternating sequence. The FPRLBs forwardly propagate signals and the BPRLBs backwardly propagate signals. Each FPRLB may receive a plurality of input signals from a plurality of FPRLBs in the preceding leftward column. Moreover, each FPRLB may output a plurality of output signals to a plurality of FPRLBs in the next rightward column.