Patents by Inventor William H. Clifford

William H. Clifford has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and methods exchanging data between processors through concurrent shared memory
    Patent number: 10691612
    Abstract: A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a plurality of media processors through separate translation table information. In particular, a page directory for a given media application is copied to a media processor's page directory when the media application allocates memory that is to be shared by a media application running on the parent processor and media processors.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: June 23, 2020
    Assignee: Intel Corporation
    Inventors: Brent S. Baxter, Clifford D. Hall, Prashant Sethi, William H. Clifford
  • SYSTEM AND METHODS EXCHANGING DATA BETWEEN PROCESSORS THROUGH CONCURRENT SHARED MEMORY
    Publication number: 20190114266
    Abstract: A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a plurality of media processors through separate translation table information. In particular, a page directory for a given media application is copied to a media processor's page directory when the media application allocates memory that is to be shared by a media application running on the parent processor and media processors.
    Type: Application
    Filed: October 12, 2018
    Publication date: April 18, 2019
    Inventors: Brent S. BAXTER, Clifford D. HALL, Prashant SETHI, William H. CLIFFORD
  • System and methods exchanging data between processors through concurrent shared memory
    Patent number: 10102141
    Abstract: A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a plurality of media processors through separate translation table information. In particular, a page directory for a given media application is copied to a media processor's page directory when the media application allocates memory that is to be shared by a media application running on the parent processor and media processors.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: October 16, 2018
    Assignee: Intel Corporation
    Inventors: Brent S. Baxter, Clifford D. Hall, Prashant Sethi, William H. Clifford
  • SYSTEM AND METHODS EXCHANGING DATA BETWEEN PROCESSORS THROUGH CONCURRENT SHARED MEMORY
    Publication number: 20180253385
    Abstract: A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a plurality of media processors through separate translation table information. In particular, a page directory for a given media application is copied to a media processor's page directory when the media application allocates memory that is to be shared by a media application running on the parent processor and media processors.
    Type: Application
    Filed: March 1, 2018
    Publication date: September 6, 2018
    Inventors: Brent S. BAXTER, Clifford D. HALL, Prashant SETHI, William H. CLIFFORD
  • System and methods exchanging data between processors through concurrent shared memory
    Patent number: 9934158
    Abstract: A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a plurality of media processors through separate translation table information. In particular, a page directory for a given media application is copied to a media processor's page directory when the media application allocates memory that is to be shared by a media application running on the parent processor and media processors.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: April 3, 2018
    Assignee: Intel Corporation
    Inventors: Brent S. Baxter, Clifford D. Hall, Prashant Sethi, William H. Clifford
  • SYSTEM AND METHODS EXCHANGING DATA BETWEEN PROCESSORS THROUGH CONCURRENT SHARED MEMORY
    Publication number: 20170147505
    Abstract: A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a plurality of media processors through separate translation table information. In particular, a page directory for a given media application is copied to a media processor's page directory when the media application allocates memory that is to be shared by a media application running on the parent processor and media processors.
    Type: Application
    Filed: December 22, 2016
    Publication date: May 25, 2017
    Applicant: Intel Corporation
    Inventors: Brent S. Baxter, Clifford D. Hall, Prashant Sethi, William H. Clifford
  • System and methods exchanging data between processors through concurrent shared memory
    Patent number: 9563570
    Abstract: A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a plurality of media processors through separate translation table information. In particular, a page directory for a given media application is copied to a media processor's page directory when the media application allocates memory that is to be shared by a media application running on the parent processor and media processors.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: February 7, 2017
    Assignee: Intel Corporation
    Inventors: Brent S. Baxter, Clifford D. Hall, Prashant Sethi, William H. Clifford
  • SYSTEM AND METHODS EXCHANGING DATA BETWEEN PROCESSORS THROUGH CONCURRENT SHARED MEMORY
    Publication number: 20160188484
    Abstract: A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a plurality of media processors through separate translation table information. In particular, a page directory for a given media application is copied to a media processor's page directory when the media application allocates memory that is to be shared by a media application running on the parent processor and media processors.
    Type: Application
    Filed: July 30, 2015
    Publication date: June 30, 2016
    Applicant: Intel Corporation
    Inventors: Brent S. Baxter, Clifford D. Hall, Prashat Sethi, William H. Clifford
  • Systems and methods exchanging data between processors through concurrent shared memory
    Patent number: 9122577
    Abstract: A method and apparatus for matching parent processor address translations to media processors'address translations and providing concurrent memory access to a plurality of media processors through separate translation table information. In particular, a page directory for a given media application is copied to a media processor's page directory when the media application allocates memory that is to be shared by a media application running on the parent processor and media processors.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: September 1, 2015
    Assignee: Intel Corporation
    Inventors: Brent S. Baxter, Prashant Sethi, Clifford D. Hall, William H. Clifford
  • Accessing memory using multi-tiling
    Patent number: 8878860
    Abstract: An embodiment of the present invention is a technique to control memory access. An address pre-swizzle circuit conditions address bits provided by a processor according to access control signals. A data steering circuit connects to N sub-channels of memory to dynamically steer data for a memory access type including tiled and untiled memory accesses according to the access control signals, the conditioned address bits, and sub-channel identifiers associated with the N sub-channels. The tiled memory access includes horizontally and vertically tiled memory accesses. An address post-swizzle circuit generates sub-channel address bits to the N sub-channels using the conditioned address bits and according to the access control signals and the sub-channel identifiers.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: November 4, 2014
    Assignee: Intel Corporation
    Inventors: James Akiyama, William H. Clifford
  • SYSTEMS AND METHODS EXCHANGING DATA BETWEEN PROCESSORS THROUGH CONCURRENT SHARED MEMORY
    Publication number: 20140075129
    Abstract: A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a plurality of media processors through separate translation table information. In particular, a page directory for a given media application is copied to a media processor's page directory when the media application allocates memory that is to be shared by a media application running on the parent processor and media processors.
    Type: Application
    Filed: November 14, 2013
    Publication date: March 13, 2014
    Applicant: Intel Corporation
    Inventors: Brent S. Baxter, Prashant Sethi, Clifford D. Hall, William H. Clifford
  • Systems and methods exchanging data between processors through concurrent shared memory
    Patent number: 8667249
    Abstract: A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a plurality of media processors through separate translation table information. In particular, a page directory for a given media application is copied to a media processor's page directory when the media application allocates memory that is to be shared by a media application running on the parent processor and media processors.
    Type: Grant
    Filed: January 6, 2009
    Date of Patent: March 4, 2014
    Assignee: Intel Corporation
    Inventors: Brent S. Baxter, Prashant Sethi, Clifford D. Hall, William H. Clifford
  • Memory micro-tiling request reordering
    Patent number: 8332598
    Abstract: According to one embodiment, a memory controller is disclosed. The memory controller includes assignment logic, a reorder table and a transaction assembler. The assignment logic receives a request to access a memory channel and assigns the request to access one of two or more independently addressable subchannels within the channel. The reorder table includes two or more table elements. Each table element includes a shared address component and an independent address component corresponding to each of the two or more independently addressable subchannels. The transaction assembler combines the shared and independent address components in a reorder table element and issue a single memory transaction.
    Type: Grant
    Filed: June 23, 2005
    Date of Patent: December 11, 2012
    Assignee: Intel Corporation
    Inventors: James Akiyama, William H. Clifford, Paul M. Brown
  • Memory micro-tiling
    Patent number: 8010754
    Abstract: According to one embodiment, a memory controller is disclosed. The memory controller includes assignment logic and a transaction assembler. The assignment logic receives a request to access a memory channel. The transaction assembler combines the request into one or more additional requests to access two or more independently addressable subchannels within the channel.
    Type: Grant
    Filed: January 20, 2010
    Date of Patent: August 30, 2011
    Assignee: Intel Corporation
    Inventors: James Akiyama, Randy B. Osborne, William H. Clifford
  • Memory micro-tiling
    Patent number: 7765366
    Abstract: According to one embodiment, a memory controller is disclosed. The memory controller includes assignment logic and a transaction assembler. The assignment logic receives a request to access a memory channel. The transaction assembler combines the request into one or more additional requests to access two or more independently addressable subchannels within the channel.
    Type: Grant
    Filed: June 23, 2005
    Date of Patent: July 27, 2010
    Assignee: Intel Corporation
    Inventors: James Akiyama, Randy B. Osborne, William H. Clifford
  • Media Memory System
    Publication number: 20100174872
    Abstract: A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a plurality of media processors through separate translation table information. In particular, a page directory for a given media application is copied to a media processor's page directory when the media application allocates memory that is to be shared by a media application running on the parent processor and media processors.
    Type: Application
    Filed: January 6, 2009
    Publication date: July 8, 2010
    Inventors: Brent S. Baxter, Prashant Sethi, Clifford D. Hall, William H. Clifford
  • Memory Micro-Tiling
    Publication number: 20100122046
    Abstract: According to one embodiment, a memory controller is disclosed. The memory controller includes assignment logic and a transaction assembler. The assignment logic receives a request to access a memory channel. The transaction assembler combines the request into one or more additional requests to access two or more independently addressable subchannels within the channel.
    Type: Application
    Filed: January 20, 2010
    Publication date: May 13, 2010
    Inventors: James Akiyama, Randy B. Osborne, William H. Clifford
  • Mechanism for assembling memory access requests while speculatively returning data
    Patent number: 7587521
    Abstract: According to one embodiment, a memory controller is disclosed. The memory controller includes assignment logic and a transaction assembler. The assignment logic receives a request to access a memory channel and assigns the request to access one of two or more independently addressable subchannels within the channel. The transaction assembler combines the request with one or more additional requests to access the two or more independently addressable subchannels within the channel and facilitates a speculative return of data from a subchannel for which a subchannel request is not available.
    Type: Grant
    Filed: June 23, 2005
    Date of Patent: September 8, 2009
    Assignee: Intel Corporation
    Inventors: James Akiyama, William H. Clifford
  • Media memory system and method for providing concurrent memory access to a plurality of processors through separate translation table information
    Patent number: 7490215
    Abstract: A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a plurality of media processors through separate translation table information. In particular, a page directory for a given media application is copied to a media processor's page directory when the media application allocates memory that is to be shared by a media application running on the parent processor and media processors.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: February 10, 2009
    Assignee: Intel Corporation
    Inventors: Brent S. Baxter, Prashant Sethi, Clifford D. Hall, William H. Clifford
  • Accessing memory using multi-tiling
    Publication number: 20080162802
    Abstract: An embodiment of the present invention is a technique to control memory access. An address pre-swizzle circuit conditions address bits provided by a processor according to access control signals. A data steering circuit connects to N sub-channels of memory to dynamically steer data for a memory access type including tiled and untiled memory accesses according to the access control signals, the conditioned address bits, and sub-channel identifiers associated with the N sub-channels. The tiled memory access includes horizontally and vertically tiled memory accesses. An address post-swizzle circuit generates sub-channel address bits to the N sub-channels using the conditioned address bits and according to the access control signals and the sub-channel identifiers.
    Type: Application
    Filed: December 28, 2006
    Publication date: July 3, 2008
    Inventors: James Akiyama, William H. Clifford