Abstract: A low resistance contact for p-type GaAs is provided by Pd/Zn/Pd/Au structure 1. The contact is suitable for device substrates having carrier concentrations in the range of about 10.sup.18 to about 10.sup.20 cm.sup.-3. The ohmic contact has a Pd layer of depth 3 nm to 15 nm, a Zn layer with a depth of between 5 nm and 40 nm, a second Pd layer with a depth greater than about 50 nm and an Au layer with a depth greater than about 300 nm. A preferred construction (1) is 5 nm/10 nm/100 nm/400 nm of Pd/Zn/Pd/Au. The ohmic contact deposition must be followed by annealing, with preferred annealing carried out at a temperature of about 200.degree. C. Annealing times are dependent upon annealing temperature, with a typical minimum annealing times of greater than 5 minutes at annealing temperatures of about 200.degree. C.