Abstract: A Phase Locked Loop system (10) provides the signals UP and DOWN for a charge pump (14). The charge pump (14) supplies a biasing signal to a voltage controlled oscillator (18). The phase and frequency relationship between a feedback signal from the voltage controlled oscillator (18) and a clock signal are used by a compensating phase-frequency detector (12) to generate the signals UP and DOWN. The pulse width of the signal DOWN is limited when a transition of the clock signal is missed. An error detector (36) provides a signal BADCLK after detecting that multiple transitions of the clock signal have been missed. The signal BADCLK generates the signal UP having a pulse width that compensates for the last signal DOWN and keeps the biasing signal to the voltage controlled oscillator (18) relatively constant when the clock signal fails.

Abstract: A circuit (70) includes a reset stage (72) and a Phase-Locked Loop (PLL) device (73). The PLL device (73) includes a phase detector (74), a charge pump (75), a filter (76), and a Voltage-Controlled Oscillator (77). The reset stage (72) receives a reference signal and is connected to the phase detector (74). The phase detector (74) receives the reference signal and a feedback signal. When the reference signal switches from a first clock signal to a second clock signal, the reset stage (72) places the phase detector (74) in an inactive state until the reset stage (72) detects a falling edge in the reference signal.

Abstract: A circuit (70) includes a reset stage (72) and a Phase-Locked Loop (PLL) device (73). The PLL device (73) includes a phase detector (74), a charge pump (75), a filter (76), and a Voltage-Controlled Oscillator (77). The reset stage (72) receives a reference signal and is connected to the phase detector (74). The phase detector (74) receives the reference signal and a feedback signal. When the reference signal switches from a first clock signal to a second clock signal, the reset stage (72) places the phase detector (74) in an inactive state until the reset stage (72) detects a falling edge in the reference signal.

Abstract: A power-on reset circuit controls a PLL to prevent overshoot of the VCO during power-up. The power-on reset circuit asserts a control signal upon detecting the power supply potential to the PLL below a predetermined threshold. The control signal enables a pull-down transistor to attenuate the control voltage to the VCO and reduce the output frequency of the VCO. The control signal further blocks the input reference signal to the phase detector. With the input reference signal blocked, the phase detector produces only down pulses to the charge pump during subsequent high to low logic transitions of the feedback signal from the VCO thereby further discharging the loop node and reducing the output frequency of the VCO. Following power-up, the control signal disables the pull-down transistor and allows the input reference signal to reach the phase detector whereby the PLL begins normal frequency acquisition and lock sequencing.

Abstract: A phase lock loop (PLL) reduces output phase jitter by averaging an input clock signal and a delayed input clock signal. A control signal selects between the input clock signal and the delayed input clock signal for providing a reference clock signal for the phase lock loop. The output oscillator signal of the PLL is divided by a predetermined integer value for providing the control signal to select between the input clock signal and the delayed input clock signal. The PLL establishes phase lock to the input clock signal during a first state of the control signal. The PLL next establishes phase lock to the delayed input clock signal during a second state of the control signal such that the average value of the output clock signal of the PLL is substantially constant.