Abstract: A microprocessor circuit including a microprocessor device and pseudo-static RAM memory further includes a switching circuit which is coupled to an NMI signal port and to a RESET signal port of the microprocessor device. The switching device intercepts an NMI signal to be applied to the NMI port of the microprocessor device and converts an initial NMI signal following a power-down or sleep mode to a RESET signal and applies the RESET signal to the RESET signal port of the microprocessor device. NMI signals which occur during normal operation of the microprocessor circuit are routed through the switching device directly to the microprocessor circuit consistent with normal operations. The RESET signal after power-down or sleep mode operations causes the microprocessor device to address ROM until after the pseudo-static RAM memory has assumed an active, externally refreshed state.