Abstract: In a level sensitive scan design (LSSD) circuit embodiment for testing the behavior of logic circuits, a mechanism is provided for generating a skewed load of data into a set of shift register scan string latches. The nature of the input scan string assures that a certain number of 0 to 1 or 1 to 0 transitions occurs as an input to the block of logic being tested. Furthermore, a mechanism for delaying by one system clock cycle time the capture of information from the logic block in a second shift register scan string provides a mechanism for testing for the occurrence of short paths and long paths while preserving testability for stuck-at faults. Furthermore, all of these advantages are achieved without impacting the traditional stuck-fault test capabilities of the level sensitive scan design methodology.

Abstract: Delays in critical signal paths are eliminated in circuits employing level sensitive scan design methods for implementing self-test operations. In particular, scan strings associataed with primary input lines are segregated and supplied to a separate distinct signature register so as to permit simplified degating circuitry on the input side of those shift register latches which are in fact associated with primary input signal lines.

Abstract: The LSSD scan paths on a number of logic circuit chips are modified and connected together in series to simultaneously serve as a random signal generator and data compression circuit to perform random stimuli signature generation.

Abstract: The LSSD scan paths of each logic circuit chip on a circuit module are connected to additional test circuit chips on the same module. The test chips contain a random signal generator and data compression circuit to perform random stimuli signature generators and also contain switching circuits to connect the scan paths of the chips in parallel between different stages of the random signal generator and the data compression means for random stimuli signature generators and to disconnect the scan paths from the signal generator and data compression circuitry and arrange them serially in a single scan path to perform other tests.