Abstract: The present invention is directed toward a system and apparatus for digitally controlling a bias control signal for at least one transistor. The present invention provides for software writable registers that control the bias control signal. The present invention further provides for the bias control signal to be temperature compensated based upon a temperature signal and a temperature profile stored in software writable registers. The present invention further provides for software control of the initialization and configuration of the bias control signal through stored program control of the values in the software writable registers.

Abstract: A circuit arrangement automatically sets quiescent collector current conditions for a class A/B RF power transistor, which is configured of a plurality of parallel-connected transistors formed in a common semiconductor die. The biasing circuit arrangement includes a temperature-sensing transistor having its collector-emitter current flow path coupled with a programmable constant current source. A differential amplifier circuit is coupled to the base and emitter electrodes of the temperature sensing transistor, and generates a bias voltage for biasing each of the transistors of the RF power device. This bias voltage is combined with a programmable D.C. offset voltage. The values of the constant current and D.C. offset voltage are programmed such that the average of the quiescent collector currents of the parallel-connected transistors of the RF power transistor corresponds to the quiescent collector current through the temperature-sensing transistor.

Abstract: An RF power FET amplifier is designed using parasitic resonant matching to reduce low intermodulation distortion. An input inductor is connected in parallel with the capacitance of the common-source input capacitance, an output inductor is connected in parallel with the common-source output capacitance. Feedback provided by the common-source capacitance between gate and drain is utilized to improve linearization and stability. The field effect transistor is designed so that the feedback signal resulting from the feedback capacitance is 180.degree. with respect to the forward gain.