Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for the dynamic power control of a memory device thermal sensor. In some embodiments a memory device includes an on-die thermal sensor and enable logic to dynamically enable or disable the on-die thermal sensor. In some embodiments, the on-die thermal sensor senses thermal data responsive to a thermal data sense indication. The thermal data sense indication may be received subsequent to the expiration of a delay period.

Abstract: In some embodiments, a chip includes a scheduler, transmitters, receivers, and control circuitry. The schedule schedules signals to be transmitted outside the chip and the transmitters transmit the scheduled signals outside the chip. The receivers receive signals including signals with temperature information related to a temperature outside the chip. The control circuitry selectively limit a number of commands that can be scheduled within a series of smaller windows while checking the temperature information near the conclusion of a larger window comprising many smaller windows. Other embodiments are described.

Abstract: In some embodiments, a chip includes a scheduler, transmitters, receivers, and control circuitry. The schedule schedules signals to be transmitted outside the chip and the transmitters transmit the scheduled signals outside the chip. The receivers receive signals including signals with temperature information related to a temperature outside the chip. The control circuitry selectively limit a number of commands that can be scheduled within a series of smaller windows while checking the temperature information near the conclusion of a larger window comprising many smaller windows. Other embodiments are described.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for the dynamic power control of a memory device thermal sensor. In some embodiments a memory device includes an on-die thermal sensor and enable logic to dynamically enable or disable the on-die thermal sensor. In some embodiments, the on-die thermal sensor senses thermal data responsive to a thermal data sense indication. The thermal data sense indication may be received subsequent to the expiration of a delay period.

Abstract: An apparatus for time-multiplexing a thermal sensor includes a digital-to-analog converter. The digital-to-analog converter provides an output to a comparator. The thermal sensor also provides an output to the comparator. A sequencer selects one of several input values to be applied to the digital-to-analog converter input. The sequencer further selects one of several latching devices to latch the output of the comparator. Once the result of the compare operation between the output of the thermal diode and the output of the digital-to-analog converter is latched, then the sequencer selects another one of the several input values and also selects another one of the several latching devices and another comparison is made between the output of the digital-to-analog converter and the output of the thermal sensor. The sequencer continues to select from among the several input values and corresponding latching devices in a rotating fashion.

Abstract: An apparatus for time-multiplexing a thermal sensor includes a digital-to-analog converter. The digital-to-analog converter provides an output to a comparator. The thermal sensor also provides an output to the comparator. A sequencer selects one of several input values to be applied to the digital-to-analog converter input. The sequencer further selects one of several latching devices to latch the output of the comparator. Once the result of the compare operation between the output of the thermal diode and the output of the digital-to-analog converter is latched, then the sequencer selects another one of the several input values and also selects another one of the several latching devices and another comparison is made between the output of the digital-to-analog converter and the output of the thermal sensor. The sequencer continues to select from among the several input values and corresponding latching devices in a rotating fashion.

Abstract: An address translator for use in a system having a central processing unit, a graphics controller for generating graphics addresses which index a graphics memory address map and for feeding data to a visual display, and a system memory converts a graphics address to a system address within the system memory. The invention initially partitions the system memory into a dedicated system memory for use by the graphics controller and a non-dedicated system memory for use by the central processing unit. The dedicated system memory corresponds to a base assigned memory within the graphics memory address map, and the non-dedicated system memory corresponds to a portion of the graphics memory address map excluding the base assigned memory. If the graphics address is within the base assigned memory, the graphics address is translated to a corresponding system address within the dedicated system memory.

Abstract: A memory controller which can be used with an external tag RAM is disclosed. Existing index registers in the controller serve double duty as buffers for storing tag RAM data during a test mode. Input/output lines for the external tag RAM are coupled to the index registers in addition to being coupled to a comparator for comparison with an external address during normal operation. A buffer is provided so that data from the external address from the CPU can be written through these same tag RAM input/output lines in order to update the tag RAM after a miss. In order to prevent DRAMS from putting data on the memory bus during a cache RAM test, a CAS inhibit signal is provided to the DRAM state machine. Posted writes are also disabled to avoid interference with the address provided to the tag RAM.