Abstract: A variable impedance circuit for use in an external circuit is disclosed. The impedance value is selected by an external circuit. The variable impedance is generated between two terminals which are accessible for connection to external circuitry. The impedance provided between these terminals is determined by a control circuit responsive to electrical signals coupled to the control circuit. An internal register in the control circuit stores a value which specifies the impedance between the two terminals. The stored value is copied into a programmable nonvolatile read-only memory in response to a first predetermined electrical signal. Similarly, the value stored in the read-only memory is selectively copied into the internal control circuit register in response to a second predetermined electrical signal.

Abstract: An integrated testing apparatus provides bidirectional coupling of a high voltage either from an internal source on an integrated circuit to a first external pin on the integrated circuit package, or to the output point of said internal source of high voltage from a voltage source external to the integrated circuit package that is coupled to said first external pin, said coupling occurring in response to an enabling signal externally impressed on a second external pin on said integrated circuit package. The testing apparatus is substantially transparent to normal integrated circuit operation when said enabling signal is removed from said second external pin.

Abstract: An integrated circuit system for generating a regulated high voltage tunneling pulse whose voltage level varies as a function of the voltage level needed to initiate tunneling of electrons across one or more dielectric gaps between respective first and second regions. The voltage level of initial electron tunneling is compared with a predetermined voltage margin so as to cause said generated tunneling voltage pulse to have a voltage level equal to the sum of said detected tunneling voltage and said voltage margin. The tunneling voltage pulse is then maintained substantially at this level for a predetermined duration before the tunneling pulse is discharged.

Abstract: A process for forming an electrical contact region between layers of polysilicon with an integral polysilicon resistor during the fabrication of MOS integrated circuits is disclosed. The contact region which does not require critical alignments, may be formed directly over an active channel or buried (substrate) contact. A silicon nitride mask is formed at the location of the contact region on the first polysilicon layer thereby allowing a thick oxide to be grown on the remainder of the substrate. After removal of the silicon nitride mask, a second polysilicon layer is formed which contacts the first layer at the contact region and defines the resistor. A doping step is used to establish the resistance of the resistor. The process permits the fabrication, by way of example, of a static (bistable) MOS memory cell employing polysilicon loads with an area of approximately 1.5 mils.sup.2.

Abstract: An integrated circuit, metal-oxide-semiconductor (MOS) static random-access memory (RAM) with a power-down mode is described. The bistable memory cells employed in the memory include low conductivity, depletion mode transistors used as loads. "Zero" threshold voltage devices are employed on a low body-effect substrate to permit the powering-down of many circuits in the memory without affecting circuit performance. Several circuits employing these zero threshold devices are described.

Abstract: A process for fabricating narrow silicon members from a polycrystalline silicon layer, such as gates for MOS field-effect transistors. The edge of a mask is used to define a gap which exposes a narrow line on the underlying silicon layer. A doped region is formed in the silicon layer through the gap and then the layer is selectively etched. The critical dimensions of the fabricated silicon members are determined by the extent of diffusion of the dopant and are substantially independent of masking tolerances.

Abstract: A process and method for accurately defining polycrystalline silicon patterns from a masking member. The critical dimensions of the silicon patterns are controlled by a diffusion step. Self-limiting etching is achieved through use of an etchant which discriminates between doped and undoped polycrystalline silicon. The process which provides significant advantages in production processing, permits fabrication of narrower gates and smoother edges on elongated silicon strips.