Abstract: A computer-implemented method for planning. The method includes assessing market attractiveness and competitiveness of an idea and planning to implement the idea. Planning to implement the idea includes predicting results based on implementation of the idea, creating a plan, and automatically re-predicting results of implementing the plan. The method also includes outputting the plan.

Abstract: In a programmable controller of the type including a microprocessor having output address terminals, output address lines extending to external addressable devices, input/output bi-directional data terminals and means for applying a binary status code made up of binary signals on the data terminals at a preselected time during a cycle of the microprocessor and indicative of the type of machine cycle to be processed by the microprocessor there is provided a system for energizing a hardwired logic circuit in response to a status code and logic on said address lines.

Abstract: There is provided a programmable controller comprising a standard microprocessor having output address terminals and input/output bi-directional data terminals and means for providing a binary code on the data terminals indicative of the status of the machine cycle to be processed by the microprocessor. This programmable controller includes a logic decoder means for producing a selected signal in response to logic signals on selected address terminals and in the status binary code of the data terminals. In addition, the programmable controller includes means for programming the HOLD state for the microprocessor. There is also provided an arrangement for expanding the number of interrupt conditions which can affect the INTERRUPT state of the microprocessor in the programmable controller.

Abstract: A system for providing digital data representative of a selected analog signal on the data lines of a programmable controller using a central processing unit. The system employs a conversion circuit which converts the input analog signal to digital data on output data terminals upon receipt of a conversion signal simultaneously with an analog signal and which creates a completion signal when the conversion is completed. The system can use at least two analog inputs that receive at least two analog conditions and convert a selected one of the analog conditions to an analog signal. Upon actuation of one of the input modules, the selected analog signal of the selected module is directed to the conversion circuit. After conversion, the conversion completion signal of a conversion circuit then deactivates the actuated input module for the next conversion cycle.

Abstract: There is provided a programmable controller comprising a standard microprocessor having output address terminals and input/output bi-directional data terminals and means for providing a binary code on the data terminals indicative of the status of the machine cycle to be processed by the microprocessor. This programmable controller includes a logic decoder means for producing a selected signal in response to logic signals on selected address terminals and in the status binary code of the data terminals. In addition, the programmable controller includes means for programming the HOLD state for the microprocessor. There is also provided an arrangement for expanding the number of interrupt conditions which can affect the INTERRUPT state of the microprocessor in the programmable controller.

Abstract: There is provided a programmable controller comprising a standard microprocessor having output address terminals and input/output bi-directional data terminals and means for providing a binary code on the data terminals indicative of the status of the machine cycle to be processed by the microprocessor. This programmable controller includes a logic decoder means for producing a selected signal in response to logic signals on selected address terminals and in the status binary code of the data terminals. In addition, the programmable controller includes means for programming the HOLD state for the microprocessor. There is also provided an arrangement for expanding the number of interrupt conditions which can affect the INTERRUPT state of the microprocessor in the programmable controller.

Abstract: A system for monitoring the logic conditions at the external addressable locations of a programmable controller wherein intermediate memory units are provided for controlling separate input and output locations. The controller periodically sequences the data in the intermediate memory units to maintain the logic conditions in the input and output locations. If the logic conditions are to be updated, the controller obtains access to the sequencing arrangement and changes the logic conditions within the intermediate memory units. Thereafter, the sequencing continues to maintain the desired logic conditions in the input and output locations.