Patents by Inventor William Hallberg

William Hallberg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11909129
    Abstract: System including a dual-fed antenna element is designed to present 2×2 port impedances that guarantee high efficiency operation of the main- and auxiliary transistors at peak- and backed off power. The proposed solution eliminates the need for lossy power combining, such as PCB based circuit combining or impedance matching networks between the antenna element and the main- and auxiliary amplifiers. The power from the main- and auxiliary transistors are combined at the circuit level by the antenna element.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: February 20, 2024
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Christian Fager, William Hallberg, Oleg Iupikov, Marianna Ivashina, Rob Maaskant
  • Publication number: 20210296776
    Abstract: System including a dual-fed antenna element is designed to present 2×2 port impedances that guarantee high efficiency operation of the main- and auxiliary transistors at peak- and backed off power. The proposed solution eliminates the need for lossy power combining, such as PCB based circuit combining or impedance matching networks between the antenna element and the main- and auxiliary amplifiers.
    Type: Application
    Filed: May 31, 2018
    Publication date: September 23, 2021
    Inventors: Christian FAGER, William HALLBERG, Oleg IUPIKOV, Marianna IVASHINA, Rob MAASKANT
  • Patent number: 9614479
    Abstract: It is provided an amplifier arrangement for optimizing efficiency at a peak power level and a back-off power level ?. The amplifier arrangement comprises an input power splitter dividing an input signal into a first signal having a power Pm and a second signal having a power Pa, a main transistor operating in a class-B like mode receiving the first signal, an auxiliary transistor operating in a class-C mode receiving the second signal. The received first and second signals have a phase offset value ?, wherein ??<?<?. The amplifier arrangement further comprises a combining network.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: April 4, 2017
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: William Hallberg, Mustafa Özen, Christian Fager
  • Publication number: 20170005620
    Abstract: It is provided an amplifier arrangement for optimizing efficiency at a peak power level and a back-off power level ?. The amplifier arrangement comprises an input power splitter dividing an input signal into a first signal having a power Pm and a second signal having a power Pa, a main transistor operating in a class-B like mode receiving the first signal, an auxiliary transistor operating in a class-C mode receiving the second signal. The received first and second signals have a phase offset value ?, wherein ??<?<?. The amplifier arrangement further comprises a combining network.
    Type: Application
    Filed: July 1, 2015
    Publication date: January 5, 2017
    Inventors: William Hallberg, Mustafa Özen, Christian Fager